Design And Implementation Of High-speed FIR Filter Based On FPGA

With the development of digital technology, digital filter occupys anirreplaceable position in signal processing field.especially, it was indispensable inspeech processing, image processing, HDTV fields and so on. Digital filter couldhave the filter meet amplitude and phase characteristics of the special requirements,and its features would not be affected when the temperature or voltage changed.Especially the filter’s advantage that system stability, hign-speed operation, highsignal-to-noise ratio, linear phase characteristics, agile design made it widely used inactual engineering.FPGA, Field Programmable Gate Array,based on LUT internal logic unit, agilewiring, rich embedded resources, particularly suitable for the data processing bigscale and high degree of parallel structure of the FIR filter realization. Because ofthe insufficient of traditional distributed algorithm in speed and resourcesoccupation,a new algorithm that combining distributed algorithm based onpartitioning technology and WALLACE TREE algorithm is adopted. This algorithmcan effectively reduce the use of multiply accumulator and save resource. Real-timeinteraction between FPGA and computer, made parameter configuration and dataanalysis and display more agile, fast depending on USB serial interface technology.This paper conducts the test and performance analysis to validate the systemthrough the SEED-XDTK FPGA platform. The experiment of high-speed FIR filterbased on FPGA proof that it can reduce11%of the Slice resource consumption andthe critical path delay is shrunked by26.9%compared with the traditional distributedalgorithm. Achieving the design goal that higher speed FIR digital filter processing,lower resources consumption.it is convenient for parameter configuration, can meetthe rapid and large amount of data processing,and filtering effect is good.