Implementation Of Digital Down Conversion And Digital Synchronization Technology Based On FPGA

Digital down conversion(DDC)and digital synchronization technology are important technologies in the field of communication.They are widely used in the second generation mobile communications(2G),third generation mobile communications(3G),fourth generation mobile communications(4G)and new generation mobile communication systems.They are the basis and core technology of wireless communication signal processing,and are the precondition of the follow-up steps of signal demodulation,deciphering and decoding.FPGA is a parallel high-speed programmable digital signal processing chip,which is widely used in communication,equipment,medical and aerospace fields.The technology of DDC and digital synchronization based on FPGA have high engineering application value.Based on the theory of digital down conversion and digital synchronization,this thesis studies the technology of digital down conversion and digital synchronization based on FPGA.1.In channelized receivers,when the bandwidth of single signal is narrower than that of system,the filter design directly using FPGA usually needs higher filter order,which is not conducive to engineering implementation.Firstly,the channelized digital down conversion is realized in the form of variable carrier,and then the data speed is reduced in the form of direct connection of CIC,half-band and FIR three-stage filters,which effectively avoids the high complexity of high-order filter design.The simulation analysis and programming test show that the method can effectively reduce the order of the filter,and then reduce the number of logical resources used in engineering implementation,and the accuracy of DDC is effectively improved.2.Digital synchronization technology is the key and difficult technology of digital signal processing,and digital phase-locked loop technology based on FPGA is the key technology to achieve digital synchronization and demodulation.Based on the engineering implementation,this thesis realizes the digital synchronization technology on the existing FPGA platform.Firstly,the engineering difficulties of carrier synchronization technology areanalyzed,and the working principles of phase discriminator,loop filter and numerical control oscillator are introduced in detail.Then,according to the analog phase-locked loop technology,the implementation steps of common digital phase-locked loop in FPGA are given.Finally,the method is simulated and verified on the high-performance FPGA platform.Theoretical analysis and programming experiments show that this method can effectively realize carrier synchronization technology,and has stable and reliable performance.