Design And Simulation Of FIR Digital Filter Using FPGA/CPLD

FPGA and CPLD are more and more extensively used in digital signal processing systems instead of ASIC or DSP chips. The digital signal processing systems based on FPGA/CPLD chips have higher real-time performance. They can be embedded into other systems. They also can implement a system on a chip and extend functions easily. This paper uses the direct structure of FIR digital filter as the implementation architecture of the circuit. The architecture mainly includes several basic circuits as following: delay unit, multiplier circuit, adder circuit and controller unit. The paper presents a multiplier circuit based on Booth algorithm when the radix equals four by studying the Booth algorithm. The carry-save-array adder and the pipeline technique are drawn into the design for improving the circuit speed. The design of the hardware multiplier circuit uses Foundation Series of Xilinx Company as the EDA tools and uses the schematic and VHDL language as the input ways. A 16 multiply 16 binary complement multiplier hardware circuit is accomplished in the paper. The results of simulation prove that the multiplier works correctly. The frequency of the hardware multiplier may go up to 30 MHz, this high-speed multiplier may be used as a basic arithmetic unit of DSP systems. A 33 order low-pass FIR filter is designed in the paper by using the hardware multiplier circuit as the basic arithmetic unit. The accumulation process of the sum and the carry of the multiplier is put to the end of the FIR operation. This 33-order FIR filter can run at 30 MHz clock rate, and the results of simulation are same to the software operation results. The improved implementation scheme of the FIR filter is described in the paper. By increasing the number of the pipeline, the FIR filter's working frequency can go up to 50 MHz. This will be more valuable in high real-time performance fields.