Design And Implementation Of FPGA-based Kalman Filter

Continued advancing in today’s technology and the rapid development of integrated circuits leading to a big technological progress. Now we can make tiny chips that have a small system placed in, which have make it very convenient for people to use. Modern signal processing system mixes Signal Theory, VLSI Technology and Computer Technology together, and plus the development of microelectronics technology, we get a very strong support during the implementation of DSP integrated circuits. The design and implementation of Kalman filter is a very noticeable subject in the digital signal processing system, and its arising give a new approach for the development of filtering.In this paper, the deduction procedure of Kalman filter were showed elaorately, and the calculation method also be analysised in detail during the design of the Kalman filter process. The first step is to create a status equation by state-space method, and then in accordance with the principle of minimum mean square error to derive the Kalman filter equations, after that based on the five recursive Kalman filter equations design how to apply the Kalman filter into practical engineering, then implementation.In the design process, the main use of Verilog HDL hardware description language design, recursive division of the Kalman filter equations into five small module, then the module combination treatment. Among them, the Kalman filter algorithm on data issues were selected, all of the data in this article using IEEE754floating point standard, the accuracy of the data to ensure that there is a great addition, as used in all IEEE754floating point standard, so the module handle used during the data selector, in order to achieve the data rate to ensure a stable output results. Kalman filter is based on the theory, the practice engineering requirements, design and implementation of the Kalman filter, which involves the decomposition filter modules, such as input and calculation coefficient representation reasonable choice coefficients. The final selection of FPGA devices, and analyzed by Modelsim, simulation waveforms, the impact of changes in the measurement noise and process noise observed on the Kalman filter and filter processing, the Kalman filter with the theoretical value through Verilog HDL simulation design coincide the results show that the Kalman filter can be designed to achieve a good filtering. This topic is designed with Cyclone Ⅱ EP2C35F673C6to make an implementation, and proved the correctness of function with the Matlab simulation.At the same time, the Kalman filter uses IEEE Standard for Binary Floating-Point Arithmetic to make calculation. Compared to the best FPGA and Verilog HDL realize for Kalman filter, the standard which it obey is the longest. In the early we need52clock cycles to complete the calculation and output data, but latter we shorten it to36clock cycles to meet the common and in the actual project and high-speed requirements.