Multi-functional Real-time Clock Generator Asic Design

This paper presents the ASIC former design of a multifunctional and real clock generator, and elaborates the processes of developing submicron and deep submicron first introduces systematic structure of the clock generator, then divides the clock generator to several parts, after completing the design with behavioral levels RTL level language description and simulation, puts the design synthesized to gate level and simulates it to validate if the function is right or not This also is the flow of TOF桪OIYN circuit design. From the result we can conclude that the design can be used in other design in the way of IF soft core or FIRM core...