Study On The Digital Phase-locked Loop And Detection Circuit Of Active Power Filter

With the application of power electronic equipments in industry and daily life widely, the grid harmonics pollution which is caused by the equipments is more and more serious. As is well known APF (Active Power Filter, APF) is one of the most effective means to solve the problem of harmonic pollutions and reactive compensation. But the application of APF is not reached maturity stage in our country, and there are still a lot of problems to be studied and to be solved. Therefore, this dissertation studies on harmonics-detector. These studies have important significance on the extensive use of the products of APF.In this thesis, common management strategies of power harmonic controling are introduced firstly, and the superiority and reliability of the APF used on power harmonic control and reactive power compensation are also described, and the foreground of digital phase-locked loop in harmonic detection method are also described. Afterwards, the dissertation analyzes the harmonic detection algorithm, parameter and dynamic performance of digital phase-locked loop, the control of sampling and so on.Through comparing the advantages and disadvantages of common harmonic current detection algorithm such as traditional fourier transform, improved Fourier series method, Fryze time domain algorithm, harmonic current detection algorithm based on Instantaneous Reactive Power Theory, the dissertation In allusion to three-phase three-wire circuit, and Two approaches for measuring harmonic current are researched in detail and Simulation model for verifying the algorithm was established. The algorithm is selected as harmonic detection algorithm of APF based on its fast detection speed, not affected by the distortion of the voltage.In addition, the structure and principle of digital phase-locked loop are studied intensively in this thesis, and the advantages and disadvantages of the traditional Phase-locked Loop and Digital Phase-locked Loop are compared and analyzed as well. It is formulated that the AD sampling control be realized by DPLL based on its none zero drift and temperature drift, strongly anti-interfere ability, good filter capacity. DPLL based on FPGA is designed, and the simulation wave is provided.Besides, the structure and principle of digital phase-locked loop is studied intensively in this paper, on this basis, the overall implementation program of the harmonic current detection system is designed. Two-CPU structure is adopted on the harmonic detection system. As the main processor, the Digital Signal Processor (DSP) is responsibility to implement harmonic current detection algorithm. Complex Programmable Logic Device (FPGA) as the auxiliary processor is designed for data acquisition control and the peripheral logic control of the system. A16-bit,6-channel, high performance and simultaneous sampling Analog-to-Digital Converter is used to ensure the real-time and precision of data collection. Finally, the simulation and experimental results is presented. The experimental results show that the harmonic detection system has an excellent performance.According to the research contents and wok that have done above, a summary and some existing shortages are given at the end of the thesis, which show the future effort working towards.