The Design Of CLB-PVCI Bus Bridge

The design of SOC usually adopts hierarchical on-chip-bus architecture, different IPs are integrated on different types of buses. Bus bridge can realize communication between the different IPs which integrated on different buses of the SOC.The CLB bus is a kind of on-chip system bus which is usually used to connect IPs with high speed and high data width.The peripheral bus that conform the PVCI standard usually used to connect IPs with low speed and low data width.The work of this dissertation is to complete the RTL design and verification of CLB-PVCI bus bridge after studying and analyzing the CLB bus protocol and PVCI protocol. The complete works include as the following.1.Study of the CLB bus protocol and the PVCI protocol;2.The design of CLB-PVCI bridge architecture;3.The design of each functional module, include the state machine, the address decoding and peripheral IP selection module, datapath module.4.The RTL simulation of the CLB-PVCI bridge.The research and practice of this dissertation complete the design of a bus bridge module which between the on-chip system bus and the peripheral bus. We also accumulated experiences to study the common methodology of designing the on-chip bus bridge.