The Research On Design Methodology Of Several Peripheral Soft IPs In 8086-based Single-Chip PC

ITRS expected that semiconductor technology scale would enter 45-nanometer era in the year of 2010 and more than one billion transistors would be integrated into a Single chip.According to this trend,all circuit modules(except monitor and keyboard)of single PC can be integrated in a chip,which is the single-chip computer.The research in this thesis is based on the project of the minimum set of 8086-based Single-Chip PC.In this paper the author adopted the IP/SoC design methodology and designed two important peripheral IPs-programmable peripheral interface a8255 IP and programmable peripheral interval timer a8254 IP.These two IPs are fully instruction-level compatible with 8255 chip and 8254 chip.Then the integration verification of them into a single-chip computer platform is realized.In order to increase testability and debuggability of the platform,this paper also discussed boundary-scan technique and designed the boundary-scan circuit-JTAG debugging module.The experimental results show that both the two peripheral IPs and JTAG debug module can well meet the design requirements.The main work and achievements are as follows:1)A kind of 8086 CPU-based single-PC platform architecture is discussed and design of two peripheral IP cores a8255 and a8254 are implemented.Independent functional verification of them and it integration into the minimum set of Single-Chip PC platform is also discussed;2)Design of JTAG debug module based on IEEE 1149.1 standard is presented to afford test and debug interface for Single-Chip PC.