Research On IP Integration Scheme And Design Of DFI-AXI Bus Bridge

In general, IP integration in SOC is implemented through system bus and peripheral bus connection. While a large number of IPs, whose bandwidth requirement is between the available bandwidth of system bus and peripheral bus, are integrated into SOC, will encounter the following problems, that the performance of system bus will be reduced if a large number of these IPs connect system bus directly and the peripheral bus is often difficult to meet the bandwidth requirement of each IP. As a result, integration of this kind of IP becomes a difficult problem in SOC design.This paper analyzes the technical requirements of integrating this kind of IP. And a design of DFI-AXI bus bridge is proposed with which this kind of IP can access the system bus indirectly.The design of interface between the DFI-AXI bus bridge and IPs, named DFI, is introduced. The signals, timing, flow control mode, data forwarding mode, and frame structure of DFI interface is designed. Through carring control information in the frame header and using virtual base address, reduce the number of interface signals and simplifys the design of interface connecting IPs to DFI-AXI bus bridge.According to the characteristics of DFI and AXI, the circuit structure of the DFI-AXI bus bridge is proposed, which maps virtual base address to the actual base address by using the lookup table, enables bandwidth allocation by using cell division and packet embedded Round-Robin scheduling method, improves the system bus bandwidth utilization by using multi-transaction processing and write data prefetching strategy, allowing multiple IPs to send data to system bus devices via DFI-AXI bus bridge by sharing bandwidth.RTL-level description of DFI-AXI bus bridge circuit-structure is proposed and the test bench is set up for the function simulation by using Modelsim software. Simulation waveforms of modules show that all modules work well to meet the design functions. The whole design simulation indicates that DFI-AXI bus bridge can allocate different bandwidth to different IPs and through the DFI-AXI bus bridge several IPs could send data to the system bus devices correctly in the way of sharing the bandwidth. The bandwidth utilization ratio of system bus is up to 80%. The design meets the requirement of IP bandwidth, and simplifies the design of the external interface, realizing the IP integration in SOC.