Key Technologies Research And Chip Design For CMOS Low Phase Noise Wideband PLL

Wireless terminals based on software-defined radio(SDR)can be dynamically reconfigured to save the cost of mobile terminals by integrating multiple communication standards into a single chip.As an indispensable part of wireless communication,transceiver system has always been a research hotspot and a difficulty in design.Therefore,the research and design of SDR transceiver is an important means and inevitable choice to reduce the cost and realize the miniaturization and universalization of wireless communication system.The chip implementation of CMOS low phase noise wideband phase-locked loop(PLL)can not only meet the technical requirements of wideband frequency hopping,but also further save the power consumption and cost of transceiver system,and realize the miniaturization and universalization of the whole SDR transceiver.Therefore,it is of great theoretical significance and practical value to explore the key technology of CMOS low phase noise wideband PLL for promoting the development of wireless communication system.This dissertation is dedicated to the key technology research and chip design of CMOS low phase noise wideband PLL.Based on 55 nm CMOS process,the design and wafer verification of a 4～8 GHz wideband voltage-controlled oscillator(VCO),a 4～8 GHz wideband frequency divider chain,a 0.5～1 GHz wideband programmable divider,a 50 MHz phase frequency detector(PFD)and charge pump(CP)and a 0.0625～4 GHz wideband PLL system are completed in this paper.The first step of PLL design is the selection of system structure and the determination of loop parameters,which is not only related to the frequency range,spur and phase noise performance that PLL can achieve and the required cost and power consumption,but also related to the complexity of the system and the feasibility of design.In this paper,the research status of wideband PLL systems at home and abroad is reviewed,and several common core PLL system structures and PLL frequency extension technologies are summarized.After analyzing and comparing the advantages and disadvantages of these structures and technologies,the structure of fractional-N PLL based on delta-sigma modulator(DSM)and the frequency expansion technology based on frequency division are determined.A wideband PLL system architecture based on frequency expansion divider and in-loop prescaler module multiplexing is proposed,which saves chip area and power consumption.Based on the theoretical analysis of spur,phase noise and loop parameters,the PLL system is modeled in frequency domain and time domain respectively by using Simulink tool in Matlab.The optimal loop parameters are found through iterative simulation,and the design indexes of each module are further determined.Thus,the feasibility of the system scheme is verified.As the core module of PLL system,VCO determines some key performance such as the output frequency range and out-of-band phase noise of PLL system.In this paper,the overseas and domestic research status of VCO is summarized,the advantages and disadvantages of several common VCO structures are compared and analyzed,and the structure of NMOS cross coupled LC VCO is finally determined.A tuning range extension technology based on multi-core multi-switch capacitor array is proposed,and based on the detailed analysis of the noise contributions of various components in the oscillator,especially the current source,a phase noise optimization technique in a wide tuning range based on second harmonic filtering and quality degeneration is proposed.Based on the above analysis,combining the structure and parameter optimization of the inductors,variable capacitors and switched capacitor arrays in each VCO core,a four-core LC-VCO array is designed and implemented in this paper.The measured results show that the tuning range of the proposed VCO array is 3.66～9.95 GHz,and the phase noise at the frequency offset of 1 MHz is-127.5～-116.8 d Bc/Hz.The high-speed divide-by-2 frequency divider in the PLL feedback loop reduces the frequency of the high frequency signal output by VCO and sends it to the programmable divider,thus is one of the necessary modules of the PLL system in this paper.In addition,the designed divide-by-2 frequency divider is also used in the wideband divider chain to expand the PLL output frequency range.In this paper,the advantages and disadvantages of several common frequency divider structures are compared and analyzed,and the structure of static current mode logic(SCML)is finally determined.A switching buffer technology of cascaded inverters and Cascode is proposed,which takes into account of driving capability and isolation requirements,and can save power consumption at the same time.Based on the above analysis,a 4～8 GHz programmable wideband frequency divider chain constructed by cascade of 6-stage divide-by-2 frequency divider combined with the corresponding switching buffer circuit is designed and implemented in this paper,and the first 3 stages are shared with the inloop prescalers of PLL.The measured results show that the proposed frequency divider chain can achieve 2/4/8/16/32/64 frequency division,and the frequency division range is 1～12 GHz under the 0 d Bm input power.Programmable frequency divider divides loop feedback signal into the same frequency signal with reference clock and then sends it to PFD.It is an important module of PLL system in this paper to realize continuous adjustable frequency divider ratio.In this paper,the advantages and disadvantages of several common programmable frequency divider structures are compared and analyzed,and the structure of programmable frequency divider based on the dual-modulus frequency divider and pulse/swallow(P/S)counter is finally determined.A true single-phase clock(TSPC)flip-flop structure based on embedded logic gates and laststage clock delay technology is proposed,which is used in the dual-modulus frequency divider to further improve the circuit speed and avoid the generation of glitches.Based on the above analysis,a 0.5～1 GHz wideband programmable frequency divider is designed and implemented in this paper.The measured results show that the proposed programmable frequency divider has a frequency range of 0.3～5.9 GHz at 0 d Bm input power.According to the frequency and phase difference between the reference clock signal and the output signal of the feedback divider,PFD and CP provide a stable DC tuning range for VCO through the loop filter,thus are important modules in the PLL system in this paper.Several common PFD and CP circuit structures are analyzed in detail,and their advantages and disadvantages are compared.Then,the adopted edge TSPC-triggered PFD structure is determined,and a CP structure with high linearity and wide output voltage range that can work in the triode region is proposed by utilizing the clamp characteristic of the operational amplifier.Based on the above analysis,a 50 MHz PFD and CP cascade circuit is designed and implemented in this paper.The measured results show that the phase detection range of the proposed PFD is [-1.94π,1.94π],and the charge and discharge current of the proposed CP is adjustable in three levels with an output voltage range greater than 0.5～2.15 V.In addition,the DSM mudule in fractional-N PLL is designed and implemented in this paper.The advantages and disadvantages of different DSM structures are compared.And the traditional MASH high-order DSM structure is improved by treating the carry output of the accumulator as random jitter to improve the periodicity of the output sequence,thereby achieving better noise shaping effect and less spurious.Based on the above analysis,the comprehensive performance of the improved MASH 1-1-1 DSM is verified by behaviorallevel simulation using Simulink tool,and the circuit realization of DSM applied in 0.0625～4GHz wideband PLL system is given in this paper.Finally,the layout and cascade mode of each module in PLL system and how to reduce the coupling between signals and the influence of the bond lines are discussed in detail,and a grounding scheme is proposed that uses the M6 layer large area metal as the reference ground plane to reduce signal interactions.On this basis,the integration of the 0.0625～4 GHz wideband PLL system is completed.The measured results show that the output frequency range of the PLL system is 0.0625～4 GHz,and the phase noise at 1 MHz frequency offset is-146.41～-199.2 d Bc/Hz,meeting design requirements for wideband and low phase noise.