| With the development of communication technology,the data transmission rate is getting higher and higher,which promotes the wide application of high-speed transmission SerDes.The increase of SerDes speed has led to an increasing limitation of channel bandwidth on speed.The use of low-bandwidth PAM4 signals can further improve the speed of SerDes,which has attracted the attention of scholars and experts in related fields and is a new hot spot in the field of high-speed SerDes research.Receiving PAM4 signals requires a new receiver architecture to accurately identify the 4 levels of the PAM4 signal,however the decoding process of the PAM4 signal increases the power consumption of the receiver,and the smaller level spacing of the PAM4 signal increases the bit error rate.This thesis takes the PAM4 decoding circuit,clock and data recovery circuit and equalizer in the PAM4 receiver as the research object with the requirements of low power consumption and low bit error rate.This paper will carry out the work in the following aspects:First,the accurate,low-power decoding method of PAM4 signal is studied.Compared with the conventional PAM4 receiver based on level shift,the amplitudedetection based PAM4 receiver has fewer comparators and lower power consumption.However,when the amplitude-detection based PAM4 receiver decodes the PAM4 signal,the amplitude detection circuit is susceptible to interference.In this thesis,the PAM4 decoding circuit based on the amplitude detection architecture is proposed in conjunction with the common mode voltage stabilization circuit,and the adaptive threshold voltage adjustment is used to achieve stable amplitude detection.The common-mode voltage stabilization circuit eliminates the change of the commonmode voltage of the input signal,which can effectively reduce the influence of the common-mode voltage change on the amplitude detection;and the appropriate threshold voltage is obtained by detecting the top and bottom positions of the output eye diagram of the amplitude detection circuit,which can accurately determine the signal swing and avoid the interference caused by different input signal amplitudes.The simulation results show that the PAM4 decoding circuit can reduce the interference received by the amplitude detection circuit and accurately decode the received PAM4 signal into a 2-bit NRZ signal.Second,CDR(Clock and Data Recovery Circuit)with fast locking and low output jitter is studied.CDR is an important module in SerDes responsible for recovering the clock from the received data.Because the conventional dual-loop CDR shares circuits such as low-pass filters,it is difficult to take into account fast locking and low output jitter,and the PAM4 signal will introduce unique data-related jitter,resulting in increased output jitter.In this thesis,a CDR with dual independent loops is proposed to cooperate with a multi-band VCO,and the jitter of the input PAM4 signal is suppressed by reducing the loop bandwidth to achieve fast locking and low output jitter of the CDR.The multi-band VCO can reduce the VCO gain while ensuring the frequency range of the VCO,and reducing the VCO gain can reduce the CDR loop bandwidth and suppress input jitter.By separating the two loops,the bandwidths of the two loops can be designed separately to achieve fast locking in the frequency-locking stage and low output jitter in the phase-locking stage.The simulation results show that CDR can quickly complete the recovery of low jitter clock and data.Third,high-speed,low-power equalizers is studied.Equalizer is an important module in SerDes that is responsible for compensating for signal attenuation during channel transmission.CTLE and DFE are two common equalizers,which are usually used jointly in receivers to combine the advantages of the two equalizers.The high gain of the limiting amplifier in the adaptive adjustment CTLE structure of the traditional spectrum balance method is difficult to achieve at high speed,which limits the circuit speed,and the conventional PAM4 DFE has the disadvantage of highpower consumption.In this thesis,the data sampler is used to replace the limiting amplifier in the conventional adaptive CTLE structure to avoid the speed limitation of the limiting amplifier,and the 1/4 rate data samplers are used to further reduce the speed limit;In addition,this thesis adopts an architecture based on amplitude detection,which can reduce the power consumption of DFE by reducing the number of flip-flops,and using the gray code after decoding the PAM4 signal as the feedback signal of the DFE.The simulation results show that the conventional adaptive CTLE has poor performance in high-speed circuits,and the proposed adaptive CTLE has better equalization effect.In addition,according to the comparison with similar structures,the proposed DFE has lower power consumption.Finally,this thesis realizes the overall structure and layout of the 56 Gbps PAM4receiver on the 55 nm process.The signal is input to the receiver after 8d B attenuation.The simulation results show that the eye heights of the three eyes of the final equalized PAM4 signal eye diagram are 163 m V,181 m V and 172 m V respectively,and the four levels can be clearly distinguished;The clock peak-to-peak jitter is 1.7ps,and the MSB and LSB data peak-to-peak jitter are 13.5ps and 13.8ps,respectively.Simulation results show that the receiver has good overall performance. |
