TCAD Simulation Of Single Event Latch-up And Upset Effect In FinFET Devices

Single-event effect generated in active area of semiconductor devices bombarded by high-energy particles in space radiation environment is the important factor affecting the reliability of spacecraft.With the development of Digital integrated circuits,chips' feature size reduced to sub 20 nm,the traditional planar MOSFET(Metal-OxideSemiconductor Field-Effect Transistor)structure is no longer applicable due to the short channel effect,while Fin FET technology has become the mainstream due to its perfect performance.Meanwhile,the difference of gate control ability,structure and layout between Fin FET and planar devices results in a change in the sensitivities of SEL(Single-Event Latch-up)and SEU(Single-Event Upset).In this paper,by finite element TCAD(Technology CAD)simulation,based on the Geant4 simulation results of the deposited-energy distribution in silicon by heavy ions,the SEL and SEU effects of Fin FET devices were investigated.The main results are as follows:Firstly,the phenomenon that the peripheral circuit of Fin FET devices was more sensitive to SEL than planar devices was studied,and based on which,a new SEL protection method was proposed.Compared with Planar devices,Fin FET devices have some differences in the structure of MOSFETs(well width,MOSFET spacing,and STI depth).By TCAD simulation,the relationship between the variation of Fin FET structure and SEL sensitivity was present.From the perspective of parasitic resistance,the reasons for the variation of the holding voltage,the trigger charge,and the current gain of the parasitic SCR(Silicon Controlled Rectifier)with the structure of Fin FET were explained.In addition,because the ratio of parasitic horizontal to vertical resistances has a difference between Fin FET and planar devices,it was found that the SEL prevent effectiveness of decreasing guard ring spacing and epitaxial substrate technique would be weaker.Based on the analysis of the influence of parasitic resistance on SEL sensitivity,two methods to prevent from SEL by reducing parasitic vertical resistance were proposed.By TCAD simulation,the effectiveness of these methods was verified.Then,the impact of the distance between transistors and well boundary in Fin FET devices on the SEU cross section of SRAM(Static random-access Memory)cell was studied.The development of semiconductor devices leads to the continuous improvement of layout integration: from 32 nm planar process to 20 nm Fin FET process,the distance between sensitive nodes(off-NMOS drain and off-PMOS drain)in SRAM and P-N well boundary decreases from 90 nm to 40 nm.The Fin FET DFF(D Type FlipFlop)model was established by TCAD simulator to analyze the impact of the transistors and well boundary spacing on the SEU cross section.The results showed that the builtin electric field,which was located at the well boundary,could absorb the electrons and holes generated by heavy ions in P well and N well to the adjacent N well and P well respectively,which could compete with the charge collection in the sensitive nodes and generate restore current in on transistors,thus inhibiting the SEU sensitivity of the device.Due to the difference between SEU cross sections per bit,compared with the low LET(Linear Energy Transfer)ion irradiations,this well boundary effect was more obvious under high LET ion irradiations.With the increase of layout integration,the distance between MOSFET and well boundary was shortened,and the boundary effect was enhanced.In addition,for FINFET devices,each generation reduction in feature size resulted in a reduction of approximately 30% in the Metal Pitch,which leaded to a further increase in layout integration and the shortening of the distance between transistors and the well boundary.TCAD simulation analysis showed that this change resulted in an approximate proportional reduction of the SEU cross section.Finally,the reason for different SEU cross section bias dependence of Fin FET devices under different LET ion irradiations were studied.The relevant experimental results showed that the cross section of high LET ion irradiations increases slowly with voltage decrease,while for low LET ion irradiations,the SEU cross section of Fin FET devices increased rapidly.Through TCAD simulation,the impacts of critical charge,collected charge,the built-in electric field in well boundary and the bipolar effect on SEU cross section bias dependence were studied.Our study results state that: under low LET ion irradiations,the change trend of collected charge with ion locations is the main reason for different SEU bias dependences,while the well boundary built-in electric field can enhance the bias dependence;under high LET ion irradiations,the change of sensitive area by the decrease of critical charge is not obvious,and the change of PMOS and NMOS sensitive area overlap with voltage is mainly responsible for the bias dependence.In addition,according to the sensitive area maps of SRAM cell,it was also found the inhibiting effect of on-NMOS drain on SEU sensitivity and the self-LEAP(Layout Design through Error-Aware Transistor Positioning)phenomenon around the well boundary of the SRAM cell,which have important reference value for SEU mitigation design.In this paper,the physical mechanism of SEL and SEU in Fin FET devices under different parameters was presented.On this basis,some more suitable SEL and SEU protection methods were proposed,and the physical processes affecting SEU cross section bias dependence of Fin FET devices were revealed.These results provide the theoretical foundation for the hardening designs of Fin FET devices.