The Design Of 25Gb/s Optical Receiver Analog Front-end Equalizer And Limiting Amplifier

The coming of the data technology era requires higher capability of data storing,processing and transmitting.The challenges on the storage and the data processing are well settled as technology scales down,whereas the data transmitting speed still falls behind which becomes the bottleneck of the big data era.Accordingly,optical commucication system has developed rapidly,which has been utilized widely for the merits of broad bandwidth and low attenuation.Optical receiver is of great importance in the entire optical system.In addition,front-end amplifier is the front part of optical receiver,which makes front-end amplifier an even more critical reasearch topic.With increasing data rates,the inter-symbol interference arising from the non-ideal characteristics of chanels such as high-frequency loss,reflection,crosstalk and noise,is the key factor that affects the further improvement of data rates.Compared to developing new materials,connectors and improving packaging technology,the enhancement of the I/O circuits' ability to compensate for signal distortion on the basis of low-cost connection is more cost-effective.In addition,since the channel characteristics are unknown or time-varing,adaptive equalization has become a research emphasis.Continuous time linear equalization(CTLE)structure is used as equalizer because of its simple structure and small chip area.The limiting amplifier(LA)structure is applied because of its simple structure and low power consumption.So we use the structure of limiting amplifier to design the main amplifier module of the optical receiver.In this paper,based on jazz 0.18 um Si Ge Bi CMOS process,the circuit and layout of equalizer and limiting amplifier in the analog front-end circuit of 25 Gbps optical receiver are designed.The simulation is carried out by virtuso and spectre software on cadence platform.The simulation results show that the continuous time linear equalizer can achieve 0-10 d B gain adjustable;thegain of limiting amplifier is up to 36 d B,the input sensitivity is less than15 m Vpp,and the output is up to 400 m Vpp,which meets the design requirements.