Research And Design Of Fractional Frequency Division Frequency Synthesizer In RF Transceiver

Frequency synthesizer (FS) is an important building block of radio frequency (RF) transceiver frontend system. Its performance determines some key parameters of the RF transceiver. In order to generate desired signal according to system requirements, the voltage-controlled oscillator in the phase-locked loop (PLL) FS is controlled by feed-back mechanism assisted by some digital arithmetic. And the design and optimization of loop parameters and build-up modules should take each other into consideration. In order to meet the requirements of protocols such as GSM and WCDMA, the FS noise performance should be optimized from loop parameters setting and module circuits design by taking locking time into consideration. The detailed achievements are as follows.The system architecture and linear model of??fractional-N PLL FS are reviewed. And the requirements of FS from RF transceiver in different applications are analyzed.In order to meet the requirements of noise performance and loop stability, a low noise LC VCO is designed. And the capacitors'size which guarantee constant VCO gain (Kvco) and constant difference of sub-band frequency are calculated with a simplified method. A simplified double-?inductor model is used in on-chip inductor description and Q factor optimization. A Q factor optimized differential varactor structure is presented. The low noise VCO was implemented in the SMIC 0.13?m 1P8M MMRF CMOS process. When oscillating at 6.35 GHz the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is-120.14 dBc/Hz. The figure of merit (FOM) of the proposed VCO is-192.13 dBc/Hz.The adaptive resolution AFC arithmetic is presented. The Kvco and frequency will be calibrated when the presented AFC applied in an adaptive bandwidth FS. The validation of Kvco calibration is made by analysis and simulation. The modules of the presented FS are working on the optimized operation region around reference voltage after locking. On that region the current of charge pump matches well and the Kvco varies little. Then the nonlinearity is sumpressed and the loop parameters are stable.A novel time-windowed phase-switching prescaler is designed, which can avoid output glitches and output pattern misunderstanding of conventional structures and is less sensitivity to PVT variety.The noise and nonlinearity of the charge pump (CP) is analyzed. Then low noise 5 GHz frequency synthesizer was fabricated in the SMIC 0.13?m 1P8M MMRF CMOS technology. When locking at 5 GHz the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at 1 MHz offset is-122.45 dBc/Hz. The 25 MHz reference spur is-69.5 dBc under the same testing condition.