CCD focal-plane image reorganization processor

Analog, charge-coupled device (CCD) signal processing circuitry for integration with an image sensor array, to reduce power and volume of downstream signal-chain electronics have been investigated. Two research areas have been pursued through the design, layout and testing of nine separate CCD integrated circuits. In the first, a charge-coupled multiplying digital-to-analog converter, and an analog-to-digital converter for focal-plane application was explored. The second and primary thrust of the work has been in on-chip real-time image reorganization for subsequent off-chip image processing.;The converters are constructed from charge-coupled circuit blocks interconnected through the wire transfer technique, realizing the first application of such an approach. The serial multiplying digital-to-analog converter is highly compact (100$mu$m x 130$mu$m), extremely low power (2$mu$W/MHz) and has demonstrated integral and differential linearity of six equivalent bits. The analog-to-digital converter implements a serial addition-based derivative of the successive approximation algorithm and has a slaved multiplying digital-to-analog converter to provide charge-domain multiplication capability.;While the majority of image processing tasks are performed on n x n (typically 3 x 3 or 5 x 5) pixel neighborhoods, conventional imagers deliver pixel data in a raster-scan sequential format. Seven integrated circuits devoted to real-time neighborhood reconstruction for off-chip image processing were designed. Six integrated circuits, consisting of a 256 x 256 buried-channel frame-transfer imager and five ICs devoted to image reorganization, were successfully fabricated and tested. Four integrated circuits providing 3 x 3 neighborhood data sequences at video rates, to enable real-time difference encoding for hierarchical image compression are demonstrated. A differential lossless encoding algorithm adapted from previously published work is presented. A fifth image reorganization chip which provides 3 x 3 neighborhood reconstruction for general purpose image processing tasks such as filtering and convolution has also been demonstrated.;Implementation of the image reformatting ICs has led to several advancements in the image sensor area. Matched, second-stage output amplifiers selected by timing have been used in an image sensor for the first time. An improved method for simultaneous access to several rows of data, utilizing shift register delay, overcomes the non-uniform charge transfer losses encountered by previously reported works. A new CCD design allowing the parallel passage of image data through several serial registers is demonstrated by ICs which have their processing circuitry integrated with a standard imager array, thus paving the way for more sophisticated focal-plane signal processing.