Research On Pixel Level Analog To Digital Conversion For Ultraviolet Focal Plane Array

Due to the “solar-blind” and “visible-blind” background, the ultraviolet detectionimaging technology is widely used in military and civil fields. The solid state UVfocal plane array imaging sensor based on AlGaN is one of the major researchdirections, which has the advantage of high quantum efficiency, no additional filter,low cost, small volume and good vibration resistance. As one of the two critical partsof the imaging sensor, including the detector array chip and the read out integratedcircuits (ROICs) chip, the ROICs are responsible for providing highly stable andaccurate bias voltages for detectors, transforming photocurrents into voltage signals,and signal amplifications. Excellent ROICs are the precondition of high qualityimaging. With the development of basic component of ROICs for ultraviolet focalplane arrays (UVFPAs), the research focus is shifted to enhance the ROICs’ abilityand improve system integration density. On-chip ADC is an interesting research area,on which the pixel level ADC is a significant part with its great signal-to-noise ratio,high frame rates, and low conversion rates.The thesis focused on the pixel level ADC research for UVFPAs. The128×128size with50μm×50μm pixel area ROIC is designed and fabricated. The developedcircuits implement the function of pixel level ADC.The paper talks about the related theoretical analysis of on-chip ADC, especiallydifferent implementation approaches of pixel level ADC. Then we establish thecircuits’ specifications, according to the characteristics of the developed UV detectorarray chip, the research trends of on-chip ADC and performance requirements of UVimaging sensor from the actual projects. The appropriate conversion methods andcircuit structures are also determined.The equivalent circuit model of the developed AlGaN p-i-n type solar UVdetector of our lab is presented. By analyzing the bias voltage control of detector, thephotocurrent injection efficiency, the area and power dissipation of the input stagecircuit, the capacitor trans-impedance amplifier (CTIA) structure is selected, to ensurethe stable zero bias voltage and up to99%injection efficiency. The noise source ofimaging sensor is discussed, and the suppression of noise from the view of circuitdesign is also presented.Firstly, the pixel level ADC for UVFPA based on a similar single-slopeconversion is proposed, with the pixel area of50μm×50μm and128×128array size. The principle and timing of this new type of analog-to-digital conversion arediscussed carefully. The theoretical derivation shows that the output number of digitalpulses represents the amplitude of input analog signals. The pixel circuit, whichintegrates an input stage circuit of CTIA structure, a comparator and a one-bit latch, iscapable of transforming photocurrents into voltage signals, digitalizing analog signalsand reading data. The image information is successfully obtained after the proposedcircuits are bonded with detector array chip using indium bump. The test results showthat an input dynamic range of70dB and11bits resolution are achieved by thedeveloped ADC.Secondly, another circuit aiming to improve frame rates and circuit precision ispresented. By using the multiple channel bit serial (MCBS) ADC method, the times ofdata read is reduced, which accelerates the imaging frame rates dramatically. Thestructure of the unique latch is discussed in details, which employs a stack oftransistors to reduce the leak current of signal information. The fitting of leak currentand number of stacked transistors is used acquire the longest hold time of informationunder available area. Theoretical analysis and simulation results show that thedeveloped circuit is effective with the accuracy of0.2mV, input dynamic range of88dB,14bits resolution and frame rates of76fps under12bits resolution and1msintegration time.To satistify the test requirements, the single board test system based on theFPGA, DAC, SRAM, RS-232, USB and voltage shift chips are designed andfabricated, which supplies low noise power and bias voltage, generates driving signalof the ROICs, receives the output data from the ROICs, and stores or uploads thereceived data. Hardware circuit design and test software design of the system areelaborated. The developed test system has noise immunity of0.3mV and13effectivebits of generated driving signals, which satisfies the requirements of the developedROICs’ tests.The developed circuits implement the function of pixel level ADC. Furtherresearch is needed on reducing power consumption and increasing data access rate.