A fully integrated 5GHz CMOS wireless-LAN receiver

Because of the demand for high data-rate wireless local area network (LAN) products, the Federal Communications Commission (FCC) released 300MHz of spectrum, known as the unlicensed national information infrastructure (U-NII) band. The allocated frequencies partially overlap the European high performance radio local area network (HIPERLAN) frequency band. In this work, a fully-integrated 5GHz CMOS wireless LAN receiver is introduced for these frequency bands.; The most commonly used receiver architecture is the superheterodyne. However, in a monolithic implementation, image cancellation is difficult due to the limitations of on-chip filters. The use of an image-reject architecture alleviates this problem to some extent. To augment the amount of image rejection beyond what is practically achieved by the image-reject architecture, a tracking notch filter is integrated with the low noise amplifier (LNA). The image-reject band of this filter is automatically tuned to the correct frequency using a low-power image-reject PLL. As a secondary benefit, the filter also reduces the noise contribution of the cascode devices in the LNA core. The receiver is implemented in a 0.24-μm CMOS technology and consumes 59mW of power and occupies 4mm2 of die area. The overall image rejection is 53dB and the noise figure is 7.2dB. The system is highly linear and tolerates large blockers.; In the receiver, self mixing of the local oscillator creates the well-known problem of DC offset. Various techniques for DC offset cancellation exist, but they all require large capacitors. On chip capacitors are crucial in analog circuit design in general, and RF design in particular. Capacitors can occupy considerable area, therefore an area-efficient linear capacitor is highly desirable. To address this problem, we propose linear capacitor structures using fractal geometries. These fractal capacitors exploit both lateral and vertical electric fields to increase the capacitance per unit area. Moreover, the capacitance density of fractal capacitors increases with technology scaling. Compared to standard parallel-plate capacitors, fractal capacitors have smaller parasitic bottom-plate capacitance. The capacitance density of the prototype fractal capacitor in this design is 3.5 times higher than a standard parallel-plate structure.