K-Band receiver front-end using a 0.18 mum CMOS technology

The expanding market for RF wireless communication systems has generated increasing interest in low cost technologies that will enable higher data rates. Although much of work has been done in increasing the data rates for WLAN applications, the narrow bandwidth remains a bottleneck. To overcome this issue, near future research will focus on the design of high frequency systems that can provide a wide bandwidth as well as lack of potential interference. With the increasing maximum usable frequency of CMOS transistors, low cost CMOS technology gradually becomes a viable candidate for high frequency applications. However, it has been difficult to design CMOS circuits at high frequencies because the parasitics due to low resistive silicon substrate prevent the realization of high performance RF circuits.; This dissertation focuses on the new design methodology to overcome the parasitic issues and implement high performance CMOS circuits at high frequencies. The significant effect of interconnects and RF pads on the frequency characteristics is discussed. In addition, it is shown that the gain of circuits can be improved by controlling the stability condition. To validate the design method, a K-Band receiver front-end for 24GHz ISM band is implemented in a standard 0.18mum CMOS process.; This receiver achieves a 26.2dB maximum gain and a 7.87dB noise figure for an RF of 24.2GHz and an IF of 5.5GHz. The measured P1dB_in of -27dBm and IIP3 of -16dBm have been obtained. The image rejection of the receiver at the image frequency of 13.2GHz is about 25.8dB. It consumes 43mA from a 1.8V supply. The measurement results show the feasibility of a standard CMOS process for high frequency applications even beyond 20GHz. The proposed design methodology and knowledge accumulated in this work provide guidance in designing CMOS high frequency circuits for low cost, higher data rate wireless systems.