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Researching And Designing Of2.4GHz CMOS LNA Based On The Negative Capacitance Circuits’ Compensation Technology

Posted on:2013-02-19Degree:MasterType:Thesis
Country:ChinaCandidate:Y C ShuFull Text:PDF
GTID:2248330374494459Subject:Signal and Information Processing
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Along with the feature dimension of the CMOS technology reducing andthe operating frequency of the circuit increasing; many parasitic parameters of thedevices which can be ignored at lower frequency, may play an important impact onthe performance of the circuit when it comes to smaller size and higher frequency;such as the gate-drain parasitic capacitance of the MOSFET. So, that is necessary toreconsider such parasitic parameters and establish a more accurate circuit model inorder to make CMOS RFIC design under deep sub-micron. At the same time, throughthe theoretical analysis we can know how much degree the parameters affection onthe key performance of the circuit. We should make a compensation when necessary.In this work, we mainly pay attention to the gate-drain parasitic capacitance ofthe common source stage of the cascode LNA under the deep sub-micron level. Wehave considered the parasitic capacitances’ Miller effect and it’s affection on theinput matching、linearity、stability and other key factors of the LNA. At the last, wemake an compensation to the parasitic capacitance an LNA with the help of negativecapacitance circuits(NCC),and gained some achievement.The first part of thesis focus on the research situation of the LNA. On the current,only CMOS technology can integrate RF front-end circuit, IF analog circuit andlarge-scale digital baseband signal processing circuit on one chip. The LNA locatedin the front-end of wireless transceiver, which is the key block of the receiver. LNA’snoise figure determines the offline of the receivers’ noise figure, and has a decisiveimpact on the sensitivity of the system.In the second part of the thesis, we mainly pay attention to the gate-drainparasitic capacitance of the common source stage of the cascode LNA under the deepsub-micron level. We have considered the parasitic capacitances’ Miller effect andit’s affection on the input matching、linearity、stability and other key factors of theLNA.The third part of the thesis, an LNA which work at ISM2.4GHz band has beendesigned with the help of negative capacitance circuits’ compensated technology. The stimulated results show that many key factors of the LNA turned out a goodperformance under the compensation of the NCC.At last, considering the layout may affect the performance of the LNA largely,we provide one kind of the layout of the LNA circuit at the final chapter.Figure26, Table10, Reference43...
Keywords/Search Tags:low noise amplifier, CMOS technology, negative capacitance, noisefigure, power consumption, gain, stability
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