A multi-gigabit CMOS transceiver with 2x oversampling linear phase detector

This dissertation presents the design of a high-speed CMOS transceiver for serial digital data. The design is based on a parallel architecture data recovery circuit. It uses multiple clock phases from a multi-phase phase-locked loop (MPLL) operating at low frequency to sample high frequency input data in a time-interleaved manner. This results in the reduction of the speed requirement for the transceiver. The new technique of time-interleaved sampling is realized by placing the analog and digital samplers alternately to sample the input data at a sampling rate of two times the data rate (2x). This hybrid parallel sampling scheme provides the input phase error to the multi-phase PLL and simultaneously recovers and deserializes the input data. The data phase detection generates the loop error signal that is proportional to the input phase error, therefore allowing the PLL to have a proportional loop control. This results in improvement of the loop stability, the output jitter, and the bit error rate over the conventional all-digital 2x oversampling, referred to as the bang-bang type phase detection. In addition, to investigate its operation closely, the model and analysis of the multi-phase PLL based on the discrete-time linear system has been developed. This model takes into account the sampling nature of the loop, which provides greater insight into the system behavior and an understanding of system constraints. The analysis shows that when the PLL loop bandwidth is much smaller than the input frequency, the system response can be approximated by the conventional continuous-time model and thus the number of phase detectors employed can be reduced. The model predicts the stability limit of the multi-phase PLL as a function of input frequency, loop bandwidth, and the number of phase detectors. In addition, the phase noise due to the bang-bang type phase detector in PLL-based clock recovery circuits has been analyzed using this model.; The design was implemented in TSMC 0.35μm CMOS. The prototype was tested with the input data rate between 1Gbps to 3.3Gbps. The introduction of numerous parasitic components in the packaging of the prototype complicated the measurement and validation of the proposed technique experimentally. The failure analysis identifies the causes as a severe noise condition in the supply rails and a resonance phenomenon of the power distribution network. The severe noise condition is due to the large parasitic inductance of the package and insufficient on-chip decoupling capacitance. Additionally, the condition was exacerbated by a change of the substrate type in the fabrication from a non-epitaxial to an epitaxial wafer. This not only defeated the noise preventive design strategy but also introduced more noise into the circuit. The large packaging parasitic inductance and the large on-chip capacitance have formed a resonance circuit that resonates with the input clock frequency. The analysis concludes that this capacitance possibly originates from either the loop filter capacitor or the capacitance between the bulk and the package cavity. Despite these manufacturing complications, transistor level simulations indicate not only the viability of this technique but also shows that the proposed implementation can work up to 3.2Gbps.