Research On Key Technology Of High Frequency CMOS Digital Phase Locked Loop

The rapid development of modern information technology puts forward higher requirements for radio-frequency(RF)communication systems.Phase-locked loop(PLL)is an essential key module in the systems thus the performance of PLL largely determines the performance of the entire system.With the development of integrated circuit(IC)manufacturing process,CMOS manufacturing process has entered a deep-submicron era,the continuous reduction in the size of process features makes the design of analog circuits more difficult,simultaneously,the advantages of digital circuits are constantly highlighted,so using digital circuits as much as possible replacing analog circuits has become an inevitable trend.Digital phase-locked loop(DPLL)has good integration,programmable flexibility,smaller size,lower power consumption and better noise performance,hence it has been widely focused on and studied.In this thesis,a high-resolution,low-power,low-noise CMOS DPLL circuit is studied and designed.Phase detection is done by an ADC-based phase detector and it includes the sampling circuit,the charge pump,the time-domain variable gain amplifier(VGA)and the SAR-ADC.The sub-sampling principle is used in the phase detection process to avoid the use of frequency dividers,the in-band noise does not need to be expanded by N~2 times and the loop noise performance is optimized.At the same time,the sub-sampling is widely used because of its high detection gain.The time-domain VGA circuit,which consists of a charge pump and a pulse generator circuit,further improves the resolution of the PLL.The SAR-ADC converts the voltage signal to a digital signal,thereby avoiding the use of analog filters that take up a large space,and instead of using digital loop filters(DLF)with a smaller-occupied space and higher flexible.Compared with traditional analog phase detectors,SAR-ADC-based phase detector saves more area and power consumption.The main contents of this thesis are as follows:1,introduce the status quo of research and development of PLL,analyze the principle,structure and main performance indicators of DPLLs,establish relevant models,and derive and analyze loop characteristics and noise characteristics;2,propose a SAR-ADC-based phase detector and make use of sub-sampling principle for phase discrimination.The phase detector of this structure,in phase discrimination process,converts the time domain to the voltage domain in the TDC phase detector of the traditional DPLLs,and it can improve the resolution of the phase detector;3,on the basis of voltage domain phase discrimination,the concept of time domain VGA is also proposed,it means the gain can be changed in the time domain.,a larger voltage accumulation is obtained by extending the charge pump operating time when the phase deviation is relatively small,which is equivalent to the gain is increased in the time domain thus to further improve the resolution of phase detector;4,analyze and design a high-precision digital controlled oscillator(DCO).The DCO uses the LC oscillator structure with the mutual coupling NMOS transistor pair.The variable switch capacitance array is divided into three tunes which are coarse,medium and fine,thus the accuracy of the DCO can be greatly improved when the range of output frequency is satisfied.Based on the TSMC 65 nm 1P9M process,this thesis adopts a top-down design method to implement a high-resolution,low-power,low-noise CMOS DPLL circuit.The main modules are:sample&hold(S/H)circuits,the charge pump,time domain VGA circuit,pulse generator circuit,SAR-ADC,DLF and DCO,etc.The simulation results are showed in the power supply voltage is 1.2 V,temperature is 27°C,tt technology,the reference clock is 50 MHz,the phase detector resolution can reach 165 fs,the DPLL frequency output range is 4.13~5.52 GHz,the center frequency is 5.09 GHz,the phase noise is lower than-113.8 dBc/Hz@1MHz,the total power consumption is 10.6 mW,the locking time is less than 10?s,and the area is 0.25 mm~2.