High-speed, low-spurious CMOS analog-to-digital converter

In spite of the increasing demand of a high-speed, high-resolution analog-to-digital converter (ADC), traditional ADCs suffer from several factors that prevent the application of such ADCs in highly demanding systems such as digital receivers. Most communication applications call for low-spurious performance from a high-speed ADC, and this research is intended to achieve high conversion rate with low spurs. This research is about the development of an ADC architecture suitable for such applications and its demonstration.; To address the speed and accuracy issues of a traditional folding ADC, two refinements are made. First, to break the speed barrier of folding ADCs, a pipelined folding architecture with odd multiples of folded signal was devised. Odd multiples of folded signals enables the use of simple folding amplifiers repeatedly in successive stages. Such folding amplifiers are pipelined with distributed track and hold (T/H) amplifiers without additional power consumption. An algorithm is developed for coding and digital error correction for a nonbinary system to generate the final digital data from each sub-ADC. The first prototype chip was designed with double-poly triple-metal 0.5 μm CMOS process within 1.68 mm2 active area. This prototype demonstrated 100 Msamples/s conversion speed with 8-bit resolution dissipating 165 mW at 5 V.; Pipelining not only provides a speed advantage, but also enables the application of background offset trimming to folding ADCs. Background offset trimming with a delta-sigma modulator is applied to compensate the random input offset of folding amplifiers. A subranging front-end is used in conjunction with the pipelined folding ADC to make the calibration feasible. The second prototype chip was measured to exhibit 40 Msamples/s conversion rate with 13-bit resolution, consuming 800 mW at 5 V.