Low power and high performance VLSI circuits for clocking systems

The clock frequency of Very Large Scaled Integrated (VLSI) Systems keep increasing with technology scaling, and System on Chip (SoC) designs will integrate tens of millions of transistors on one chip, whereas packaging and cooling designs have only a limited ability to remove the excess heat produced by the systems. All these factors result in power consumption being considered as one of the main problems in achieving high performance designs.; The power break down of a microprocessor reveals that the clocking system is one of the largest power dissipating components. It consumes 33% of the overall power of the microprocessor. The clocking system consists of flip-flops and a clock tree.; In this dissertation, low power circuit techniques including reducing the switching activity of flip flops, using dual Vdd, and using double clock edge triggering are surveyed extensively. New circuit techniques, including the conditional discharge technique, pseudo-NMOS level converting schemes, as well as the shared clocked branch technique are proposed.; Other than the clock tree, domino circuits employ the clock for precharge. The keeper for high fan in domino circuits are one of the design challenges to maintain high performance of domino while resisting the leakage. We survey the related keeper designs, and propose the differential controlled keeper technique.; With voltage scaling and threshold voltage scaling, leakage increases exponentially. We propose the external-internal dual switch leakage control scheme.; Our research methodologies consist of: SCAN (1) Survey existing research; (2) Categorize them into groups; (3) Analyze advantage and drawback; (4) New design proposal.