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Research Of Low-Power Design Technology Of High-Performance Processor Based On Clock Control

Posted on:2007-12-22Degree:MasterType:Thesis
Country:ChinaCandidate:X HeFull Text:PDF
GTID:2178360215970299Subject:Software engineering
Abstract/Summary:PDF Full Text Request
In the last few years, the performance of IC (integrated circuit) increased rapidly. With the coming of VLSI's Sub-micron era, low-power design technique has been a growing demand in VLSI design, especially in the design of general-purpose high performance processors and custom DSP chip. Low-power design technology consists of two parts: hardware low-power design and software low-power design. The paper mainly focus is hardware low-power design and its support to software low-power design.This paper first study the theory about low-power design and dynamic power management (DPM). Based on the understanding of all theses power optimization strategies, a low-power design strategy of X processor is present according to the requirement of X processor's power management and the architecture characteristic of X processor , and the key circuits, like clock gating circuit, frequency divider circuit, etc., is designed to realize low power technique. Finally, a great deal of verification work has been done based on the whole chip X processor's verification platform to prove the correction of the low power technique adopted. The main content of the paper includes:1 .Research the dynamic management(DPM) technology after the study of power consume model of CMOS circuit, and investigate methods normally used in low-power design.2. Present X processor's power management scheme according to the lower power requirement of X processor, and implement it using state machine based on X processor's clock control technology;.3. Design the key circuits to realize X processor's low power strategy, which include the circuit used to stop clock, the circuit of the microcode engine unit, frequency-dividing circuit and clock driving unit.4. Present system level verification scheme of X processor, and build the system level simulation enverioment. In the system level simulation enverioment , the correction of the state machine based on X processor's clock control technology is proved.
Keywords/Search Tags:low-power design, clock control, dynamic power management, PLL
PDF Full Text Request
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