Research On RTL-Level And Architecture-Level Key Technique Of Low Power For High Performance Processor Design

With the development of high-performance microprocessor architecture and scaling of IC technology, chip integration and frequency keep increasing. At the same time, the induced power and thermal explosion have been seriously challenging processor stability and reliability. Leakage power is increasingly becoming a major component of the power consumption of microprocessors. Without any effective control, processor will cease to improve performance, even corrupt at work.Based on the existing technologies on low power design, we focus our research on the RTL-level and architecture-level technologies. We verify the technologies on OpenSPARC T2 RTL source code, and the results come from Atrenta SpyGlass power analysis tool set and software simulation.First, by analyzing the clock gating design in the original design of OpenSPARC T2, we use several optimizing technology to enhance the clock-gated region and shut off more idle unit clocks, such as the basic clock gating, the forward trace, the forward traced with signal merged and the backward trace. Running results show that, with the same workloads for a single OpenSPARC core, these combined clock gating technologies can reduce the overall power consumption by 35%.Secondly, based on the analysis of the program's executing characters on multi- threaded processors, we propose a fine-grained temperature-aware instructions-queue scheduling technology for multi-thread processor core, which schedule the queue by taking the function units as the basic temperature sensing units. This can reduce the possibility of rapid rise of power consumption and temperature inside the processor, without obvious falling of the overall performance. Running results show that, under the same workload, the single OpenSPARC core equipped with the best configuration can reduce the number of the thermal peak by 30%, with less than 10% performance overhead losed.Finally, based on the assistant information given by the replacement algorithm in set associative Cache, we forcast that the Cache blocks which will be replaced would be used rarely, then propose an accelerated LRU replacement algorithm, through recording the Cache dynamic access information, shut off the power of Cache line as earlier as possible to reduce the Cache leakage power consumption, without obvious falling of the overall performance. Simulation results show that, this method can reduce the leakage power consumption of Cache by 69.2%, and make the overall performance of the processor reduced less than 2%.