High speed successive approximation ADC and its applications

Data converters are required in many applications such as serial link, wireless communication and clock generation circuits. For example, analog to digital converters (ADCs) are usually time-interleaved to implement very high speed ADCs in serial link and ultra wide-band (UWB) receivers. Phase to digital conversion is also a critical building block of digital phase locked loops (DPLLs). With recent advancements in speed and power consumption, successive approximation ADCs (SAR ADCs) have achieved significant attention. The focus of this dissertation is on the design of a high speed and low power SAR ADC. The main target application of our ADC is time-interleaved ADCs and DPLLs.;Several new techniques are proposed to realize a single-stage 10b 250MS/s SAR ADC. A double capacitor-array digital to analog converter (DAC) with top plate sampling enables the use of simple switch circuitry with faster settling time while improving power efficiency. The ADC also employs a two-speed variable clock generator to exploit the reduced DAC settling time requirements. A semi-dynamic comparator modified for low voltage design is used to achieve fast decision and reset times. A multiple latch based SAR logic decreases the propagation delay in the digital loop. A metastability detection circuit with minimized self-metastability window is also proposed.;With the improvements in time-interleaved SAR ADC performance, the power of the voltage buffer in the input track-and-hold amplifier (THA) driving the SAR ADC input capacitor becomes a major component of the overall power consumption. To reduce the input buffer power consumption, a switched current integrating sampler (CIS) is proposed. The switched CIS is analyzed and compared to the conventional THAs. To fairly compare the power consumption of both circuits under different operating conditions, power consumption equations are derived. Circuit level simulations are performed to validate these equations. The switched CIS is shown to consume approximately 50% of the conventional switched THA power for medium resolution (i.e., <8b) TIADCs.;Phase-to-digital converter (PDC) is one of the main building blocks of the DPLL. Low power and high speed performance of the SAR ADC makes it suitable for phase to digital conversion. In this dissertation, an integer-N DPLL that employs an analog-to-digital converter (ADC) to digitize the phase error is presented. Compared to the conventional time-to-digital converter (TDC), the proposed ADC-based PDC with the same number of bits can be shown to reduce the quantization noise contribution to the DPLL output jitter variance by more than an order of magnitude. Design examples are presented to verify the functionality and performance of the proposed approach.