| As the clock frequency and chip size of high-performance microprocessors increase, distributing clock signals across the chip becomes increasingly difficult due to increasing propagation delays and decreasing allowable clock skew. This dissertation presents the design, implementation, and demonstration of an intra-chip wireless clock distribution. The system consists of transmitters and receivers with on-chip antennas communicating via electromagnetic waves at the speed of light. A global clock signal is generated and broadcasted using a transmitting antenna. Clock receivers distributed throughout the chip detect the signal using on-chip antennas, amplify and divide it down to a local clock signal, and buffer and distribute the clock signals to the adjacent circuitry.;To synchronize all the receivers across the chip, a scheme using a transmitted global clock signal with 2-ns no transmission period and the programmable divider in receiver is proposed. The package (such as the heatsink) and on-chip metal structures can significantly affect the on-chip antenna characteristics. AlN, an insulator with high thermal conductivity is used to reduce the heatsink effects and increase the antenna pair gain ∼8dB. A general design guideline is also proposed to reduce the on-chip metal structures' impact on the antenna performance. In addition, thinning the lossy substrates to 100 mum increases the gain of an on-chip antenna pair with 1.0 cm separation by ∼15dB.;A broadband low noise amplifier (LNA) preceding the programmable divider and detector in the receiver is demonstrated using a 8-level-metal 130-nm CMOS process. It has 20 dB voltage gain at 20.6 GHz, 5.5 dB noise figure and 4 GHz 3-dB bandwidth.;An intra-chip wireless clock distribution system is successfully demonstrated using on-chip antenna pairs, a clock receiver, and a clock transmitter. With 0.26-mm separation between the antenna pair, the system is working between 17 GHz and 18.7 GHz. The peak-to-peak jitter of the whole system (excluding VCO in transmitter) is 5.4ps, or ∼1.21% of a local clock period. The programming bits of the divider is also successfully demonstrated at 18 GHz. Because of the divider programmability, the maximum skew of this system should be less than 1/16 of a local clock period, which is 6.25% of a local clock period. Using an off chip power amplifier which increases the transmitter output power from 4 to 11dBm, the system is demonstrated at 2.5-mm separation between the transmitting antenna and the receiver. These measurement results demonstrate the synchronization scheme of the intra-chip wireless clock distribution system, and indicate that wireless approach can be a practical for clock distribution option in the future microprocessors. |
