A wireless clock distribution system using an external antenna

With the increase of system operating frequency and projected die size, distributing signals across the chip becomes challenging, due to the larger R-C delays, tighter skew and jitter tolerance and signal dispersion along the metal interconnect paths. Some novel interconnection architectures are under investigation to tackle these problems, including optical interconnects, superconducting interconnects and biological interconnects. Previous works have demonstrated a wireless interconnect for clock distribution system utilizing microwaves, which is compatible with the conventional CMOS process. In such a system, clock signals propagate at the speed of light of a propagating medium. An on-chip or off-chip transmitting antenna transmits a global clock signal. A grid of on-chip receivers with integrated antennas picks up the signal, amplifies it and divides it down by 8 to provide the local clock signal. This work theoretically investigates the integrated antenna performance. Using the results from this, a wireless clock distribution system using an external antenna (inter-chip wireless clock distribution) is constructed, and its characteristics are studied.; First, the gain, directivity, efficiency and impedance of dipole antennas with arbitrary length, and the power transmission gain between any two dipole antennas in a lossy medium have been calculated and used to determine approaches to optimize antenna performance at a given frequency. Second, an inter-chip wireless interconnection is constructed and measured. The feasibility of an inter-chip clock distribution system is evaluated by measuring the power transmission gain between off-chip antennas and on-chip integrated antennas, and relative gain and phase distributions of signals picked up by the on-chip antennas. Also, a commercially available heatsink with fins and rectangular apertures is incorporated into this system. Third, a 17-GHz and a 20-GHz clock signal transmitter in a UMC 0.13 mum logic CMOS process have been designed, fabricated and measured. Periodic no-signal-transmission function is incorporated in the output clock signal, which is used by clock receivers for initialization and start-up. Finally, with a horn antenna as the external transmitting antenna, the operation of the entire wireless clock distribution system is successfully demonstrated for the first time. The receiver initialization and start-up steps are working well and repeatable. The total clock skew and jitter are below 5% of a period at ∼ 2.2GHz over a 4-cm diameter circular area. The results of this dissertation show the feasibility and have the potential for opening the doors for new clock distribution systems which can operate at higher frequency and synchronize a larger area.