Time and Statistical Information Utilization in High Efficiency Sub-Micron CMOS Successive Approximation Analog to Digital Converters

In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quantizer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multilevel redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an interstage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results.;Key Words: SAR ADC, TSAR, Ternary SAR, Residue Shaping, EMCS, FITSAR, R2R DAC.