Advanced test generation techniques: Improving yield and protecting intellectual property

We identify two new directions in automatic test pattern generation (ATPG) research. In one direction, we generalize the notion of detection of a fault to only consider errors that have severities greater than a given threshold of acceptability. In another, we explore ATPG in the context of systems on chip (SOCs) that uses multiple intellectual property (IP) cores.; In [CO 02 TR] and [BG 99 MTV] it has been shown that in many applications some types of errors at outputs of many modules are acceptable as long as their severities are within given limits of acceptability. In our threshold testing research, we propose a new testing methodology, namely threshold testing, to increase yield by identifying chips that are imperfect but acceptable. The notions of acceptable fault and acceptable chip are introduced. Direct threshold testing paradigm is proposed as a viable way to carry out threshold testing. We further investigate a constrained version of the problem, where output errors are measured in terms of absolute numerical errors (ANE). An ANE-based threshold test generation algorithm is developed. Main innovative components of threshold ATPG algorithm include new ANE-based branch and bound conditions and an ANE-oriented output analysis technique. A new ATPG subtask, namely fault effect blocking (FEB), is added. One classical ATPG subtask, namely fault effect propagation (FEP), is extended. Experimental results demonstrate that our threshold testing methodology can accrue significant yield benefits with only minimal increase in test costs and test quality.; In our SOC ATPG research, we develop a hierarchical ATPG algorithm that can be used to generate customized test sets for SOCs that use multiple IP cores. Test generation hierarchy is introduced to protect IP information of core vendors. Two ATPG paradigms, namely coarse-grain and fine-grain, are proposed. A comparative study of the two proposed paradigms shows that the coarse-grain paradigm has a lower ATPG cost than the fine-grain paradigm. Experimental results demonstrate that test size and test efficiency of proposed hierarchical ATPG are close to those of a classical ATPG that can access the netlist of the whole SOC, despite that fact that little IP is revealed during proposed ATPG. Parallelism is exploited to further reduce ATPG cost of the coarse-grain ATPG algorithm.