Characterization of the mechanisms affecting single-event transients in sub-100 nm technologies

This dissertation uses both three-dimensional mixed-mode technology-computer-aided design (TCAD) simulations and experimental analysis at the 65 nm, 90 nm, and 130 nm technology nodes to fully characterize the mechanisms that affect single-event transient (SETs) in sub-100 nm bulk CMOS technologies. Chapter I introduces the motivation for this work. Chapter II presents background on single-event effects. Within the chapter, single-event effects are identified and explained in context to digital circuits. Chapter III then focuses on the specific single-event effect of SETs and the factors that influence them. In the second part of the chapter, the discussion focuses on common methods of experimental SET measurement and the typical target structures used. Chapter IV discusses the relationship between the parasitic bipolar and n-well contacts, and how it affects the pulse width of SETs. Chapter V then introduces the mechanism of pulse quenching by using TCAD simulations, heavy-ion data, and laser data, to identify pulse quenching in multiple technology nodes. Additionally the chapter explains in detail how the layout and circuit design can influence pulse quenching. Finally, Chapter VI presents simulation and experimental heavy-ion results that explain a new SET mechanism called DPSETs. Instead of a single ion strike creating a single pulse SET, a single ion strike can result in a DPSET.;The research presented in this dissertation directly impacts the SEE circuit qualification and analysis techniques used in the radiation effects community. Simulations supported by experimental data illustrate how there are new mechanisms in sub-100 nm bulk CMOS that can affect SET pulse widths. These mechanisms can negate traditional RHBD solutions, but also can be used as new RHBD solutions. Designers and researchers can use this work to better analyze SET results, and they can predict how SET pulse width will be affected in future bulk CMOS technologies. (Abstract shortened by UMI.).