Study Of Single-event Effects Of Logic Circuits In Nanometer Bulk CMOS Process

Radiation environment in space causes serious reliability problems to aerospace electronic systems.Nanometer integrated circuit has the advantages of high performance,high integration and so on,making it an essential choice for aerospace electronic systems in the future.When the feature size of integrated circuit scales to nanometer,single-event effects(SEE)are becoming the main radiation induced reliability problems.Because of the increase in transistor density,decrease in the supply voltage and increase in frequency as a result of the improvement of integrated circuits and the characteristics of coexistence of many kinds of radiation effects and a wide range of temperature in space,the challenge of researching SEE of logic circuits is increased.This thesis studies in depth the impact of inner circuit factors and two space environment variables on the production and propagation of SEE in nanometer bulk CMOS logic circuits and the responding mechanisms.The former factors include the supply voltage of circuits,working frequency and circuit layout structure while the latter variables include temperature and total-ionizing dose(TID).Regarding the principle of single-event upsets(SEU)induced soft error propagation in nanometer logic circuits,the impact of the supply voltage and frequency of circuits on the principle is studied.The model of SEU propagation probability is quantified.After taking the SEU cross section difference between master and slave latches in a flip-flop into consideration,an advanced model of SEU-induced soft error propagation is proposed,which improves the accuracy of the current model significantly.Furthermore,based on the proposed advanced model,a methodology to quantitatively evaluate the single-event soft error dynamic cross sections of flip-flop chain logic circuit is proposed by combining experiments and simulations.Regarding the impact of layout structures on SET in nanometer logic circuit,the sensitivity difference of single-event multiple transients(SEMT)between guard-ring hardened and commercial layout structures is studied.By varying the incident angles and tilting angles of heavy ions,energies of pulsed laser and supply voltages of circuits,the effectiveness of guard-ring hardened layout design in suppressing SEMT production is verified.Thanks to the different charge sharing processes between angled and normal incidences of heavy ions,significant different distributions of SEMT pulse width are observed in these two irradiation conditions.Regarding the impact of TID on SEEs of nanometer logic circuits,the impact of the supply voltage and the circuit input test bench on single-event soft error cross section as a function of TID is studied.For the first time,an increase in single-event error cross sections of logic circuits followed by a decrease in cross sections as a function of TID is observed.A decrease in effective driving current of transistors and an increase in logic gate delay time as a result of TID irradiation explains the experimental phenomena observed.Regarding the impact of temperature on SEEs of nanometer logic circuits,the change of single-event soft error cross section of logic circuits as a function of temperature is studied at different supply voltages.At the relatively high and relatively low supply voltages,for the first time,different trends of SEU-induced soft error cross section as a function temperature are observed,which is attributed to the “reversed temperature effect”;at the relative high supply voltage,SET-induced soft error cross section is found to be more sensitive to temperature variation than SEU-induced soft error cross section because of the latching window effect of SET.