| Phase-locked loops (PLLs) are an important building block of almost any synchronous digital system. However, unlike digital design, the design of phase-locked loop circuits remains a manual and time-consuming process. The manual design flow often requires multiple, costly silicon iterations in order to meet the specifications. In contrast, by reusing algorithms and methodology across process technologies, digital design automation has reduced the design time and design risk issues to that of accurate process modeling. Moving forward, phase-locked loop design, and analog circuit design in general, must follow a similar evolution.; We describe in this work an efficient, robust, and repeatable design flow for clock generation and clock synchronization phase-locked loop (PLL) circuits via geometric programming (GP). A simple, fully-automated process to generate device models in a form compatible with GP is described, which includes equations to model the physical process information. Equations for the power, stability, frequency range, jitter, static phase error, and acquisition time of the PLL are presented in GP form. Arrays of PLL circuits were automatically generated using this technique in both 0.18mum and 0.13mum CMOS processes. Silicon measurements show good agreement with the model. The results include a 0.18mum, 1.9GHz PLL with a period jitter of 2.2ps RMS and an accumulated jitter of 6.2ps RMS, consuming 10.8mW from a 1.8V supply. The results also include a 0.13mum, 1.4GHz PLL with a period jitter of 4.3ps, an accumulated jitter of 5.4ps, and a power consumption of 11.1mW from a dual 1.2 V/2.5V supply. The techniques described within form a robust, systematic, and process portable design methodology for complex analog circuits with competitive performance. |
