High speed, high resolution and high SFDR analog-to-digital converter architecture and design

The feedforward residue compensation (FRC) architecture combines a Nyquist rate A/D converter with an over sampled converter. A digital calibration technique that allows the FRC architecture to provide high resolution at high sampling speeds is introduced. In particular, a practical ADC architecture using a digital gain error calibration technique provides a 15-bit 70-M Samples/s converter with greater than 100 dB SFDR. This architecture extends the resolution of high performance state-of-the-art pipeline ADCs by 2-bits of resolution. The high performance pipeline ADC is used as an auxiliary converter in the FRC architecture and an over sampled converter acts as the primary converter. The primary converter adds additional bits of resolution to the auxiliary converter. A technique presented for digital correction of gain error allows for a practical implementation of the architecture. Both MatLab simulation results and prototype testing are used to verify and quantify the architecture.; Results from a test chip fabricated in the TSCM 0.18u process is used to validate the design. Measurement results for a 70 Msps, 15-bit ADC show a signal-to-noise (SNR) of TBD and a SFDR of TBD.