| Radio architecture design has changed with developments in digital signal processing and data conversion, allowing the commercialization of the wideband software programmable radio receivers. These developments have allowed architectures whose frequency channels and protocols are programmable and can be defined in software. This is especially relevant for wireless base-stations, where it offers significant benefits: reducing the cost, size, complexity, and power consumption of a base-station. More importantly, it can support a variety of air/modulation schemes and protocols.; These high performance receivers place very stringent demands on the analog-to-digital converter (A/D). This thesis focuses on the design of a high speed and high spurious free dynamic range ( SFDR) analog-to-digital (A/D) converters for cellular base station applications.; Pipeline A/D are particularly suited for this application. The nonlinearities in a pipelined A/D converter have a repetitive or periodic nature, which results in the generation of spurious tones in the frequency spectra of the converter output. Some of the non-idealities that affect the SFDR performance of the pipeline converters include, but clearly is not limited to, the amplification techniques, capacitor matching, and reference voltage variations. This design includes various circuit level and system level correction techniques to address the nonlinearity and gain issue in the various blocks of the pipeline A/D converter.; At the circuit level the correction techniques have been applied to the sample and hold (S/H) amplifier, which is one of the most critical blocks. At the system level, a dynamic noise cancellation-continuous gain correction (DNC-CGC) technique has been designed to correct for the nonlinearity and gain error in the digital-to-analog sub-converter of the first pipeline stage, which is the most dominant error in this A/D architecture.; Results from a discrete prototype and a fabricated chip (TSMC 0.25mu) are used to validate the design. Measurement results for a 50Msps, 14 bit pipelined A/D converter show that the signal-to-noise (SNR) increases from 44dB to 71 dB and that the SFDR increases from 51dB to 96dB, using the DNC-CGC calibration technique. |
