| Demand for high-performance analog-to-digital converter (ADC) integrated circuits (ICs) with optimal combined specifications of resolution, sampling rate and power consumption becomes dominant due to emerging applications in wireless communications, broad band transceivers, digital-intermediate frequency (IF) receivers and countless of digital devices. This research is dedicated to develop a pipelined and subranging based architecture with minimum power dissipation, while keeping relatively high speed and high resolution.;Different from typical pipelined and subranging ADCs, the proposed novel structure is constructed with multi MDACs, multi residue amplifiers and a circular resistive interpolation network. In order to remove the gain error caused by the inaccurate open-loop gain, relative comparison method is employed. Digital correction technique performs in this project not by reducing the residue swing to half, but by enlarging the reference range dynamically. On the basis of the original architecture, various stage partition schemes have been explored according to thermal noise distribution, capacitor matching, linear error contribution and speed and power trade off consideration to optimize the overall performance.;As verification of the proposed design methodology, a 12-bit l00MHz analog-to-digital converter prototype and a two-bit resolution enhancement version are developed in commercial 0.35mum BiCMOS and 0.18mum CMOS technologies, respectively. Sorts of improved structures for the critical building blocks, such as comparator and track-and-hold, have also been studied and put into practice in different CMOS and BiCMOS processes. |
