A Study Of Direct Digital Synthesis Chip With High SFDR

With the increasing development of modern communication and high-bandwidth radar system, high quality signal generator is in great demand. Direct digital frequency synthesis(DDS) is one of them because of the rapid frequency switching, stable phase and great frequency discrimination. DDS can greatly improve the ability of anti-interference and processing gain of these systems. However, it is the spurs of DDS that prevents it from replacing traditional frequency synthesizer completely. This nearby spurs can become disaster after frequency multiplying. Therefore, the research of high performance high frequency DDS is very necessary.This thesis present a interpolated DDS chip design, based on CORDIC algorithm, with a pseudo-random sequence encoder(Dither) adding to it, making it high in SFDR and speed and increasing the bandwidth. The thesis detailed discusses the principle and constructure of the DDS chip, the analysis of the CORDIC algorithm and the purious sources,thus proposing 3 methods to improve SFDR : an increase of the phase accumulator output bandwidth, Dither and interpolation techniques,as well as MATLAB model validation, ASIC function design, physical compile, physical implement and verification.A Dither is added and the bit-width of the output of phase accumulator are enlarged in the new CORDIC algorithm. As we can learn from the siulation results,the output signals of different frequencies have reached more than 110 d B at least enhance 23.7d B. The DDS chip in this thesis supports three kinds of operating modes, namely digital ramp sweep mode, Profile mode and tone mode. The results of the RTL code simulation show that the design can meet the functional requirements, and the SFDR of the output signals of different frequencies were about 100 d B.The proposed new DDS chip of this thesis is based on SMIC 0.18μm 1.8V 1P6 M standard CMOS technology library, accomplishing physical compiling and physical design.The results of the compiling shows that DDS chip has 41,570 cells, of which there are 35,950 combinational logic cells, and 5620 sequential logic cells, with a total area of 1090437.06μm2. And the dynamic power is188.67 m W, the static power consumption of only 74.47μW and the total power consumption is 188.75 m W. The time required for the critical path for 2.92 ns, we can see that the maximum frequency of a single-core DDS chip sampling clock can reach 300 MHz, thus the total sampling frequency of the system up to 1.2GHz. The physical implementation results show that the effective area of the DDS chip is 1250μm × 1250μm, total power consumption of 517.8m W. Physical analysis and static timing analysis is not a problem, after the simulation results show that the frequency 43.541 MHz for 95.057 d B, meet the high SFDR design requirements.