Design of high speed output drivers

With the explosion of Internet usage and the rising of digital signal processing circuitries speed, the high demanding volumes of data in digital telecommunication networks have ignited interest in high-speed electronic circuits. The demand for speed in data transportation between systems motivates research for faster communication channels. The digital telecommunication networks also demand minimum power dissipation while demanding higher performance. In many cases in digital circuits, CMOS devices have an advantage in power dissipation compared to other technologies (SiGe, InP, etc). For the trend of broadband transceivers integration in optical telecommunication, it is desirable to realize various output driver techniques in CMOS technology to overcome the limitations. This dissertation will demonstrate CMOS technology which can be used to realize wideband output drivers which is one of the most difficult blocks to design in an optical transceiver. A novel approach to implement low power high performance preemphasis Current-Mode-Logic output pad driver in monolithic integrated circuits is presented in Chapter III and IV. The design utilizes an analog continuous-time Finite Impulse Response Filter to reduce Inter-Symbol-Interference caused by interconnect channel's low-pass effects. The design utilizes two source-follower topologies which are a simple positive feedback and a simple feed forward approach to control both rise and fall times for a given loading capacitance. This novel technique is used to implement a differential output pad driver for the high-speed serial data/clock design in a standard 0.13 mum CMOS technology. The driver occupies less than 0.2 mm2 of die area including the area of two ball pads and can drive a 50-O load through a 50-O transmission line for higher than 12-Gb/s data rates.; Another circuit topology to implement constant gain wideband for low impedance transmission line drivers in monolithic integrated circuits is presented in Chapter V. The design utilizes Shunt-Shunt-Active-Feedback topology to attain significant increase in bandwidth and to control its gain over the temperature and the process variations. This implementation also utilized a standard 0.13 mum CMOS technology and occupies less than 0.022 mm 2 of die area. This driver can drive 50-O internal transmission line for data rates higher than 12-Gb/s.