Design of high speed MUX/DMUX using a new all-time-on single-ended CMOS logic

The continuous increase in the volume of data transfer around the world reinforces the importance of realizing higher speed optical transceivers. Developing such transceivers however is hindered by technology limits and design techniques. Manufacturers continue to improve the related technology, but these improvements require more money and more time. Research should therefore be conducted to discover new design techniques suitable for high-speed operation.; The optical transceiver is constructed of several analog and digital blocks. In order to obtain new design techniques that are appropriate for high-speed operation, the optical transceiver must be divided into smaller blocks. Then, each block should be examined to find some way to redesign it for high-speed operation. There are two key blocks in optical transceivers: the multiplexer (MUX) and the demultiplexer (DEMUX), which are responsible for converting parallel data into serial data at the transmitter input, and for converting serial data into parallel data at the receiver output.; The MUX is the first block in the transmitter that captures the original data channels to be transmitted as its inputs. This position for the MUX increases its importance, because any non-ideality in the output of this block will travel along the whole system. As a result, the quality of the MUX output strongly affects the transmitter's performance. The importance of the DEMUX is that it is the last block in the receiver that restores the received data channels to their original form. This position for the DEMUX increases its importance because it produces the final output of the system. As a result, any nonideality in the output of this block will represent the whole transceiver performance.; Researchers have focused on higher speed MUXs and DEMUXs, and derived them in several technologies and design techniques. One of the most attractive technologies is CMOS because of its low cost, high level of integration, and the continuous shrinking of its minimum gate length. In this work, 0.18 mum CMOS technology is chosen because of its availability and low cost. The maximum speed recorded with this technology using conventional design techniques is 10 Gb/s, derived by employing MOS current mode logic (MCML) for higher speed stages and static CMOS logic for lower speed stages in both the MUX and the DEMUX.; In this work, a new circuit design strategy suitable for designing high-speed digital circuits in CMOS technology is introduced. This strategy is based on sizing the conventional pull up-pull down MOS logic to keep the MOS transistor on all the time and switching it between two on-on states instead of between the on-off states, in order to achieve more speed.; A high-speed MUX and a high-speed DEMUX were realized using this new design technique to run at 15 Gb/s in 0.18 mum CMOS technology, which is 50% faster than what state-of-the-art MUX/DEMUX realized in the same technology using conventional MCML.; The fabricated 4:1 MUX demonstrates error-free running at 15.2 Gb/s and consumes 278 mW of power, while the fabricated 1:4 DEMUX exhibits error-free running at 12.5 Gb/s and consumes 332 mW. In fact, both the MUX and the DEMUX were designed to run at 15 Gb/s.; However, only the MUX was tested at this speed, while the DEMUX was tested at 12.5 Gb/s, which is the maximum speed of the available pulse generator used in the testing. The measured power consumption in the fabricated MUX/DEMUX includes the power consumption of the input buffers, output buffers, and a clock divider.