A/D converters with system embedded calibration for wireless applications

The scaling of CMOS technology has made it feasible to integrate complex digital signal processing functions in wireless transceivers. Several analog functions in communication systems are increasingly being displaced by algorithms implemented in a digital baseband processor. As a result, more stringent requirements are being imposed on the system's analogto-digital converter (ADC), which remains as an irreplaceable analog component in the signal processing chain. In addition to the need for high throughput, the growing trend toward portable devices dictates stringent upper bounds on the affordable energy per A/D conversion. This dissertation focuses on the design of an energy-efficient A/D converter as a key component within a portable wireless communication system. The proposed ADC minimizes its power dissipation through system-centric analog/digital co-design. An energy-efficient ADC architecture with simplified analog circuitry is employed to achieve power-efficient operation. The nonidealities caused by these simplifications are corrected through a digital background calibration algorithm. The distinguishing features of the proposed calibration scheme lie in the reuse of digital system resources and the exploitation of redundant features in the received signal.; In this research, the A/D converter in an ultra-wideband OFDM receiver is considered as a specific target. The core of the ADC is based on a time-interleaved array of successive approximation register (SAR) ADCs to achieve high energy efficiency at the target speed. The inter-channel offset mismatches, which are identified as the main issue in the proposed architecture, are adjusted by the proposed calibration loop. The calibration leverages the system's pilot tones as well as existing synchronization and FFT hardware blocks for calibration purposes. The robustness and speed of the calibration algorithm are analyzed and simulated to confirm the feasibility of the proposed technique.; An experimental 6-bit prototype ADC was fabricated in 0.18-mum CMOS technology and tested within the OFDM system environment. At a sampling rate of 200 MS/s, the ADC achieves an SNDR of 35.4 dB with a total power dissipation of 6.58 mW. The proposed calibration yields an SNDR improvement of 20 dB after a convergence time of 108 clock cycles.