| This dissertation focuses on the circuit design techniques for an asynchronous sigma delta Analog to Digital Converter (ADC). The key advantage of this ADC approach is the potential for dynamic range to improve with the evolution of CMOS fabrication process. In contrast, conventional synchronous sigma delta ADC does not enjoy the benefit of improved dynamic range and lower power consumption from the scaling of CMOS fabrication process. The asynchronous approach has already been proposed in the past but no actual circuit has previously been designed and implemented. As a case study, an asynchronous sigma delta ADC is designed and compared to its conventional synchronous counterpart according to Worldwide Interoperability for Microwave Access (WiMAX) communication standard. WiMAX is selected in this case because it has a wide signal bandwidth and is, currently, one of the most common research topics in wireless communication field.;Instead of amplitude to digital conversion, like a conventional synchronous sigma delta ADC, a new idea, asynchronous sigma delta ADC is adopted for the designs presented in this dissertation. This type of ADC has simpler analog circuitry than conventional synchronous sigma delta one, while taking the size and power dissipation benefits from the scaling of CMOS fabrication processes. The overall power consumption of the proposed asynchronous sigma delta ADC design is just 9.4mW, which is among the lowest compared to existing synchronous sigma delta designs.;Asynchronous Sigma Delta ADC employs a pulse-width modulation whereby the analog signal amplitude is converted to time domain then to digital words. Unlike the conventional synchronous architecture, this ADC does not suffer from the effects of excess loop delay, which typically arises from the digital to analog converter feedback circuit. Moreover, the dynamic range of an asynchronous continuous time sigma delta ADC is directly proportional to the resolution of a time to digital converter (TDC). TDC resolution depends mainly on the digital delay elements and flip-flops, thus the overall ADC performance has the potential to improve as CMOS fabrication process continues to develop.;Novel circuit elements, such as integrator, hysteresis comparator and the time to digital converter (TDC), are proposed in this dissertation for the asynchronous sigma delta ADC. The op-amp inside the integrator has 1GHz unity gain frequency, while consumes only 1.6mW from a 1.6V voltage supply. Due to inconsistent delay period in the TDC, a delay locked loop (DLL) is deployed to ensure the uniformity of the delays from each individual voltage buffer.;The idea of Asynchronous Sigma Delta ADC has been previously proposed; however, the designs presented in this dissertation provide the first circuit-level implementation of the asynchronous sigma delta ADC concept. They can also serve as a foundation for future development of asynchronous sigma delta ADC. |
