A new test metric and a new scan architecture for efficient VLSI testing

This dissertation presents three techniques that improve the efficiency of VLSI testing: gate exhaustive test set generation, test set reordering, and a new scan architecture. Experimental and simulation results are presented to demonstrate the efficiency of each technique.; Gate exhaustive (GE) testing is presented as a new test metric; a GE test set applies all possible gate input combinations to each gate and observes the gate response at an observation point. Experimental results using 324 defective Stanford ELF35 test cores show that a GE test set detects three more defective cores than a single stuck-at fault (SSF) test set and one more core than a 15-detect test set. The test set size of the GE test set is 170% that of the SSF test set and 12% that of the 15-detect test set.; Test set reordering is a technique for reducing the number of test patterns with a minimal impact on defect detection. A GE test set with 1,556 patterns is reordered using the GE test metric and the SSF test metric. The unordered test set required 758 patterns to detect 140 defective Stanford ELF18 cores. The test set reordered using the SSF test metric required 739 patterns, whereas that reordered using the GE test metric required 286 test patterns.; California scan architecture (CSA) is a scan architecture that modifies repeat-fill patterns to toggle-fill patterns during the scan shift-in operation to improve test quality and to reduce power consumption during testing. Simulation results using the b19 circuit of the ITC'99 benchmark suite demonstrate that the average number of SSFs detected per pattern of CSA is 97.9% that of traditional scan architecture (TSA) with random-fill, while that of TSA with repeat-fill is 83.0%. The power consumption of CSA is 17.8% that of TSA with random-fill, while that of TSA with repeat-fill is 10.6%.; These techniques can be combined to improve the efficiency of semiconductor chip testing. The benefits include (1) improved test quality, (2) reduced test cost, and (3) reduced power consumption during test application.