Research On Test TEchnology Of VLSI

The increasing of functions and scale in VLSI made great pressure to VLSI test. Not only the test generation is more and more difficult, but also the test application time becomes longer and longer. This increases the test expense constantly. However, the VLSI test problem relates to designing, producing, manufacturing and application developing of VLSI and other relative products in many fields. Therefore, how to find a high affection, low expense VLSI testing method to fulfill current test need is more and more concentrated by people. According to the problem of test generation time long, fault coverage low and test application time long, this dissertation takes the VLSI testing as background, deeply study the VLSI test generation method, test quality improve method and static test compact method respectively.First, the critical technologies of VLSI test generation are analyzed in detail. The circuit model and fault model of the circuit under test are established. The fault equivalence is done to the objective fault set to reduce the computation time of test generation procedure. According to the testability analysis and computing method of circuit, the testability of circuit under test is analyzed and computed. The computing result is input to the chain table structure to select the best path of test generation. The parallel fault simulator is used to select the best test set to ensure fault coverage and improve the test generation efficiency.Secondly, according to the test generation time long and fault coverage low problem of VLSI test, the better capacity algorithm ant algorithm and genetic algorithm are applied to simulation based test generation procedure to reduce the test generation time. Since the simulation-based test generation is lack of information necessary to active the objective fault and to propagate the fault effect, scan design test structure is introduced. A limit scan test generation approach is proposed base on both. Base on the simulation-base test generation method, the scan input, scan select and scan out of scan circuit are regarded as common inputs and output. The difference between scan time cycle and test time cycle is penetrated to improve the fault coverage. Experimental result and comparison result of benchmark circuits’show that the proposed approach reduced the test generation time and improve the fault coverage effectively.Thirdly, in order to improve the quality of the limit scan test sequence, and improve the fault coverage and fault isolate rate of limit scan test sequence in non-modeled fault, this dissertation analysis the current test quality evaluation method, and adds the fault isolate rate evaluation method to it. Then the new test quality evaluation method is applied to the limit scan test sequence. According to the characteristics of the limit scan test sequence, two test quality improvement approaches are proposed. By randomly specifying the unspecified value of test sequence and modifying the scan select subsequence of test sequence, the limit scan test sequence quality is improved. Experimental result of benchmark circuits show that the proposed method improve the fault coverage and fault isolate rate of limit scan test sequence in non-modeled fault effectively.Finally, according to the test sequence generated by scan design test structure long, consumes more the test application time problem, the vector omission based static test compaction is applied to the limit scan test sequence to take out the redundant test vectors. According to the scan characteristic of limit scan test sequence, a limit scan static test compact approach is proposed base on the vector omission based static test compaction. Inside the result of the vector omission based static test compaction, shorter limited scan operations are used to take place of longer full scan operations and limited scan operations. The candidate test vectors are combined and the heuristic method is introduced to reduce the computation complexity of static test compaction. Experimental result of benchmark circuits show that the proposed approach reduces the test application time and test data storage effectively and keeps the fault coverage at the same time.