DCScan: A Power-Aware Scan Testing Architecture

Nowadays, digit systems are widely used in daily life. Integrated circuit(IC) serves as the most important part in all kinds of digit systems. In recent decades, with the rapid development of very large scale integration (VLSI) technique, the density of transistors increases dramatically, which makes VLSI testing a huge challenge. Traditional methods cannot cope with the development of IC, thus the design for testability(DFT) techniques are introduced. Full-scan testing is one of the most important DFT methodologies. However, its application efficiency suffers from prolonged test application time, huge test data volume and high test power. So far, among the research works for scan testing, some of them focus on test cost reduction; others focus on how to reduce test power. Unfortunately, few methods give attention to reducing both test cost and test power. In fact, to reduce test cost, we need to enhance the parallelism of test to the circuits under test (CUT), which would results in more transitions during testing. Thus, test power is quite high.This thesis proposes a novel power-aware architecture-- DCScan based the compatibilities of the scan cells. In this architecture, there is no transition while shifting in test data. Thus test application time and test power are drastically reduced. After introducing the concepts of XOR- and NXOR-compatibilities, the extended DCScan architecture achieves lower test power and shorter test application time compared with that of DCScan architecture. Furthermore, compared to extended scan tree architecture, where XOR- and NXOR-compatibilities are also introduced, our extended DCScan architecture puts on a more efficient performance in reducing test power.Though the extended compatibilities scan tree architecture reduces test cost drastically, its wiring length is so long. Longer wiring length means extra hardware area, probably causes clock delay and route congest, which hurts the performance of CUT. To solve this problem, this thesis proposes two solutions. One is scan cells reordering and the other is to introduce a wiring length threshold so as to avoid the appearance of too long wiring. Experimental results shows that these two solutions are efficiently reduce wire length, especially the second one.