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Design and analysis of a transformer coupled CMOS receiver front end for high frequency applications

Posted on:2009-07-25Degree:Ph.DType:Dissertation
University:Arizona State UniversityCandidate:Chen, WenjianFull Text:PDF
GTID:1448390005451720Subject:Engineering
Abstract/Summary:
Due to the limited spectral bandwidth and expected saturation of existing bands below 6 GHz, the trend for next-generation wireless communications is to utilize higher frequencies for wideband communication applications to avoid spectral congestion. However, this choice requires advanced technologies to build the RF interface. Previous designs operating at higher frequency have used GaAs high-electron mobility transistors (HEMTs), which offer excellent RF performance compared to silicon (Si) metal-oxide-semiconductor field effect transistors (MOSFETs) due to their higher electron mobility, higher breakdown voltage, and the availability of high quality-factor passives. However HEMT technologies are limited by high fabrication costs and low integration densities when compared to silicon designs.;With today's scaled down CMOS transistors showing cutoff frequency exceeding 100 GHz, IC operation at tens of gigahertz frequency range with relatively inexpensive and highly integrated CMOS process is possible. However, there are major challenges to employing CMOS technologies for these high frequency applications. Innovation is needed to overcome the lower supply voltage and lower available gain at the desired high frequency band.;Inductive coupling through the use of an on-chip transformer is a promising technique for high frequency applications. In this work, a monolithic 14-GHz CMOS receiver down-converter with on-chip LO and IF bandpass filter has been proposed. Theoretical analysis on circuit performance (gain, noise and linearity) in term of transformer device parameters was performed to analyze the tradeoff of the power consumption, gain, noise figure and linearity. A simplified linearity model was developed and verified with the mathematic analysis and circuit simulation. A prototype circuit chip was design and fabricated in a 0.13 um CMOS technology; the measurement data shows an agreement with the analysis. This demonstrates that transformer employed between the transconductance stage and the switching quad stage of the receiver front end lowers down the supply voltage and also implements single to differential conversion. This may provide a compact low power, low cost solution.
Keywords/Search Tags:CMOS, High frequency, Transformer, Low, Receiver, Applications
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