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Frequency translation techniques for high-integration high-selectivity multi-standard wireless communication systems

Posted on:2001-05-26Degree:Ph.DType:Thesis
University:University of California, BerkeleyCandidate:Rudell, Jacques ChristopheFull Text:PDF
GTID:2468390014455562Subject:Engineering
Abstract/Summary:
This work examines some of the issues associated with the realization of practical single-chip CMOS receivers from both the radio architectural level as well as the issues surrounding the implementation of all-CMOS frequency-translation circuits.;From a radio architecture perspective, this thesis introduces the wide-band IF with double conversion receiver system. This receiver architecture is explored and compared to other recently proposed radio architectures which attempt to facilitate high levels integration of the analog front-end components while maintaining the overall performance with respect to sensitivity and selectivity. On a lower circuit level, a discussion is given on the implementation issues of an all-CMOS image-rejection function which utilizes the Weaver method. The system level advantages of implementing a single-chip radio are demonstrated with the introduction of a Weaver image-rejection mixer, which overcomes the traditional non-idealities of single-sideband mixers through auto-calibration techniques. The analysis and design of current-commutating Gilbert-Cell-like CMOS mixers are also examined in this thesis. A new circuit topology is introduced in this work, which generates accurate quadrature phases with minimal degradation in the carrier power, and ultimately reduces the static power required by the LO buffering circuitry.;Two high-integration all-CMOS prototype receivers were implemented using the wide-band IF with double conversion architecture. The first receiver was implemented in a double-poly triple-metal 0.6-mum Taiwan-Silicon-Manufacturing-Company (TSMC) CMOS process, and was designed to meet the specifications of the Digitally Enhanced Cordless Telecommunications (DECT) standard. This device, at the time of publication, had the highest level of radio integration in CMOS, while having the ability to operate on a higher carrier frequency (1.9 GHz) than any previously reported work while meeting the requirements of a common radio standard (DECT). This first receiver had a measured sensitivity of -90 dBm, with a power consumption of 198 mW. The second prototype receiver was designed in a double-poly five-level-metal 0.35-mum STMicroelectronics process, and targeted higher levels of selectivity performance while illustrating the multi-modal capabilities of the wide-band IF architecture. (Abstract shortened by UMI.)...
Keywords/Search Tags:Wide-band IF, CMOS, Radio, Receiver, Level, Architecture
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