| RFIC's are traditionally implemented in III--V compounded semiconductors or in bipolar technologies, due to their superior RF performances (e.g. low noise) when compared to CMOS technologies. The challenges are not only to design RF transceivers in standard CMOS processes, but also to establish design methodologies and optimization techniques for their building blocks.; This thesis is concerned with one of the key building blocks, namely the Low Noise Amplifier (LNA). Several low-voltage LNA's were successfully implemented in a standard 0.18 mum CMOS technology, operating in the 5--9 GHz frequency band, targeted for future wireless applications. A new and very simple gain control mechanism is suggested for the first time, which does not affect the optimum noise and impedance matching. The 8--9 GHz prototypes are the highest LNA frequencies reported to-date in CMOS. All prototypes exhibit gain tuning ranges of over 10 dB, and can operate from a supply voltage as low as 0.7 V.; A design strategy for optimizing RF passive components (e.g. inductors, capacitors, and varactors) beyond 5 GHz is presented.; An attempt is made to explore the possibility of using Micro-Electro Mechanical Systems (MEMS) in the RF arena. (Abstract shortened by UMI.)... |
