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Precision CMOS receivers for VLSI testing applications

Posted on:2003-10-16Degree:Ph.DType:Dissertation
University:Stanford UniversityCandidate:Weinlader, Daniel KeithFull Text:PDF
GTID:1468390011986224Subject:Engineering
Abstract/Summary:
Testing CMOS parts is becoming more difficult due to the proliferation of high-speed I/O circuits that operate at frequencies exceeding the performance capabilities of modern testers. The performance gap between high-speed chip I/O frequencies and tester frequencies is further extended by the rapid performance scaling of CMOS, compared to bipolar and GaAs technologies which are commonly used in tester electronics. Furthermore, as VLSI parts integrate increased amounts of functionality and become more complex, testing of the parts becomes more difficult due to insufficient observability of the high-speed interactions between circuits within the chip. Integrating high-speed test capabilities onto production die would permit testing of parts incorporating high-frequency I/O in addition to increasing the observability of internal signals on the die.; The key challenge is to achieve high-precision timing measurements using a process technology that may be no better than the one used to build the part being tested. To overcome the frequency limitations of the process technology, an oversampled receiver with time-interleaved samplers clocked by a multi-phase clock generator is utilized. While this enables a high receiver sample rate, sampler input offsets and static phase spacing errors in the clocks limit timing accuracy. This dissertation presents techniques to measure and compensate for static errors in both the clock generator and input samplers. In addition to static errors, jitter in the clock generator can significantly degrade timing accuracy. Therefore, a technique that measures and subtracts jitter from the timing measurements is proposed.; The aforementioned techniques enable the construction of an input receiver with timing accuracy suitable for testing applications and are demonstrated with a 0.25μm CMOS test chip. Techniques are also presented to integrate a small oversampling receiver onto VLSI parts to increase observability and enable timing measurements of internal signals.
Keywords/Search Tags:CMOS, VLSI, Receiver, Testing, Parts, Timing measurements, I/O, High-speed
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