Design And Fabrication Of Monolithic Integrated Single And Multi-channel OEIC Receiver In Standard CMOS Processes

With the rapid improvement of data amount, traditional electrical interconnection (EI) becomes non-satisfiable for huge capability. Now in the data transmission aspect, there are both electrical and optical interconnections (OI), and because of the advantages of optical interconnect, we can forecast that in the near future it will totally substitute EI. In OI system, the design of high speed, high sensitivity optical receiver is always a key point. In the past, the photodetector of optical receiver and the high speed analog circuit module were all fabricated by non-CMOS technologies, for their excellent performance with the limitation of expensive manufacturing costs and much longer design and fabrication cycle. The development of CMOS technology has promoted the photodetector and high speed front-end circuit design for OI, made it possible to integrate these two parts into one single chip, and connect them by the metal layer in CMOS process. Through this way, the parasitic effects of packaging and module connection were eliminated, the EMI and noise from outside were restrained, and also the complexity of fabrication was reduced. Furthermore, with the progress in CMOS technology, the feature size has kept shrinking, made the development of speed and sensitivity of photo receiver more rapid.This thesis focuses on the research on photodetector and TIA circuit in optical receiver. At first, the basic system structure and parameters of the receiver have been described; the principle, topology and characteristics of PD and TIA have been analyzed; the challenges and trade-off in receiver design have been discussed.In this foundation, the single channel and 12 channels parallel optical receiver have been simulated, taped out, and tested respectively, and the optical receiver module has been fabricated. In more detail, it includes:1. Several kinds of PD structures compatible with standard CMOS process have been designed and simulated, Selected structures have been taped out with CSMC( a foundary in WuXi, China) 0.6μm CMOS process and TSMC(a foundary in Taiwan, China) 0.18μm CMOS process.2. The TIA circuit of optical receiver has been designed. In the circuit design, we should trade-off between bandwidth and noise. The method of sensitivity analysis has been described, and the relation between circuit parameters and receiver's sensitivity has been found out through simulation. At the same time, new topologies of TIA circuit which use pre-equalizer to extend the bandwidth have been presented.3. According to the requirement of VSR4-1.0, the research of 12-channel parallel optical receiver has been described. In this process, the main deference to single channel is that there are inter-channel crosstalks among channels. The traditional crosstalk restrainment method of isolation has been attempted. More over, a novel way to cancel it by study crosstalk issues from circuit design perspective has been given.4. After the simulation and analysis, the overall layout of the photoreceiver has been designed, and has been taped out and tested. The results confirmed the ideas in simulation.5. The 12-channel parallel optical receiver module has been fabricated.The achievements of this thesis are that integrated the PD and TIA circuit into one single chip, implemented high speed, high sensitivity single channel and 12-channel parallel photoreceiver. It will provide valuable guides to the realization of high speed optical interconnection.