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Theoretical Study And Design Of Pre-equalized CMOS Optoelectronic Integrated Receiver

Posted on:2011-07-25Degree:MasterType:Thesis
Country:ChinaCandidate:C L YuFull Text:PDF
GTID:2178360308454676Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Compared to the hybrid-integrated photo-receiver, the monolithic CMOS optoelectronic integrated receiver not only reduces the cost of receiver greatly, but also eliminates the parasitic elements caused by packaging and interlinkage between different modules, and electromagnetic interference and noise of extra environment effectively. However, there are still many application issues to be solved because of the limitations of standard CMOS technology.Considering the shortcomings of the photo-receiver comprised of transimpedance amplifier and post-equalizer, such as complex circuit structure, big power dissipation, area cost and insertion loss, a novel method for enhancing the sensitivity and speed of receiver called pre-equalization, which compensates the transferred signal at the input port of a preamplifier, is put forward. And the corresponding system structure, theory and design method of pre-equalized CMOS optoelectronic integrated receiver are also presented detailedly, including implementation of high-speed CMOS photo-detector, theory study and circuit design of pre-equalizer and high-sensitivity transimpedance amplifier, and design methods of high-speed limiting amplifier and low-noise photo-receiver.Based on 0.35μm RFCMOS technology, three types of pre-equalized receiver are designed by parallel resonant loop pre-equalizer, third-order ladder network pre-equalizer and high-pass filter pre-equalizer, respectively, where a fingered P+/ N-well/P-substrate dual-photodiode implemented in MOSIS 0.35μm standard CMOS Process is applied with a 40μm×40μm area, a 1.1GHz 3dB bandwidth and a 0.95pF junction capacitance. The simulation results demonstrate that a maximal flat frequency response and a maximal sensitivity can be achieved by inserting a third-order ladder network pre-equalizer to a receiver, which approach 2.19GHz and -15.25dBm respectively. Finally, the receiver's layout is drawn.The achievement of the paper is that it offers a novel idea to solve the application issues of CMOS optoelectronic integrated receiver.
Keywords/Search Tags:Pre-equalization, CMOS, Optoelectronic Integrated Receiver, Peaking Technique, High-sensitivity, High-speed
PDF Full Text Request
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